linux-kernel - Re: [PATCH 11/21] PCI: designware: Make use of BIT() in constant definitions

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Date:   Wed, 26 Dec 2018 15:14:58 +0000
From:   Gustavo Pimentel <gustavo.pimentel@...opsys.com>
To:     Andrey Smirnov <andrew.smirnov@...il.com>,
        "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>
CC:     Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        Fabio Estevam <fabio.estevam@....com>,
        Chris Healy <cphealy@...il.com>,
        Lucas Stach <l.stach@...gutronix.de>,
        Leonard Crestez <leonard.crestez@....com>,
        "A.s. Dong" <aisheng.dong@....com>,
        Richard Zhu <hongxing.zhu@....com>,
        "linux-imx@....com" <linux-imx@....com>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 11/21] PCI: designware: Make use of BIT() in constant
 definitions

Hi,

On 21/12/2018 07:27, Andrey Smirnov wrote:
> Avoid using explicit left shifts and convert various definitions to
> use BIT() instead. No functional change intended.
> 
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@....com>
> Cc: Bjorn Helgaas <bhelgaas@...gle.com>
> Cc: Fabio Estevam <fabio.estevam@....com>
> Cc: Chris Healy <cphealy@...il.com>
> Cc: Lucas Stach <l.stach@...gutronix.de>
> Cc: Leonard Crestez <leonard.crestez@....com>
> Cc: "A.s. Dong" <aisheng.dong@....com>
> Cc: Richard Zhu <hongxing.zhu@....com>
> Cc: linux-imx@....com
> Cc: linux-arm-kernel@...ts.infradead.org
> Cc: linux-kernel@...r.kernel.org
> Cc: linux-pci@...r.kernel.org
> Signed-off-by: Andrey Smirnov <andrew.smirnov@...il.com>
> ---
>  drivers/pci/controller/dwc/pcie-designware.c |  2 +-
>  drivers/pci/controller/dwc/pcie-designware.h | 18 +++++++++---------
>  2 files changed, 10 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index d123ac290b9e..086e87a40316 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -300,7 +300,7 @@ void dw_pcie_disable_atu(struct dw_pcie *pci, int index,
>  	}
>  
>  	dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, region | index);
> -	dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, ~PCIE_ATU_ENABLE);
> +	dw_pcie_writel_dbi(pci, PCIE_ATU_CR2, (u32)~PCIE_ATU_ENABLE);

This is unrelated with the patch description purpose.

>  }
>  
>  int dw_pcie_wait_for_link(struct dw_pcie *pci)
> diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
> index 58735fd01668..348e91b6daa2 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.h
> +++ b/drivers/pci/controller/dwc/pcie-designware.h
> @@ -40,11 +40,11 @@
>  #define PORT_LOGIC_LTSSM_STATE_MASK	0x1f
>  #define PORT_LOGIC_LTSSM_STATE_L0	0x11
>  #define PCIE_PORT_DEBUG1		0x72C
> -#define PCIE_PORT_DEBUG1_LINK_UP		(0x1 << 4)
> -#define PCIE_PORT_DEBUG1_LINK_IN_TRAINING	(0x1 << 29)
> +#define PCIE_PORT_DEBUG1_LINK_UP		BIT(4)
> +#define PCIE_PORT_DEBUG1_LINK_IN_TRAINING	BIT(29)
>  
>  #define PCIE_LINK_WIDTH_SPEED_CONTROL	0x80C
> -#define PORT_LOGIC_SPEED_CHANGE		(0x1 << 17)
> +#define PORT_LOGIC_SPEED_CHANGE		BIT(17)
>  #define PORT_LOGIC_LINK_WIDTH_MASK	(0x1f << 8)
>  #define PORT_LOGIC_LINK_WIDTH_1_LANES	(0x1 << 8)
>  #define PORT_LOGIC_LINK_WIDTH_2_LANES	(0x2 << 8)
> @@ -58,8 +58,8 @@
>  #define PCIE_MSI_INTR0_STATUS		0x830
>  
>  #define PCIE_ATU_VIEWPORT		0x900
> -#define PCIE_ATU_REGION_INBOUND		(0x1 << 31)
> -#define PCIE_ATU_REGION_OUTBOUND	(0x0 << 31)
> +#define PCIE_ATU_REGION_INBOUND		BIT(31)
> +#define PCIE_ATU_REGION_OUTBOUND	0
>  #define PCIE_ATU_REGION_INDEX2		(0x2 << 0)
>  #define PCIE_ATU_REGION_INDEX1		(0x1 << 0)
>  #define PCIE_ATU_REGION_INDEX0		(0x0 << 0)
> @@ -69,8 +69,8 @@
>  #define PCIE_ATU_TYPE_CFG0		(0x4 << 0)
>  #define PCIE_ATU_TYPE_CFG1		(0x5 << 0)
>  #define PCIE_ATU_CR2			0x908
> -#define PCIE_ATU_ENABLE			(0x1 << 31)
> -#define PCIE_ATU_BAR_MODE_ENABLE	(0x1 << 30)
> +#define PCIE_ATU_ENABLE			BIT(31)
> +#define PCIE_ATU_BAR_MODE_ENABLE	BIT(30)
>  #define PCIE_ATU_LOWER_BASE		0x90C
>  #define PCIE_ATU_UPPER_BASE		0x910
>  #define PCIE_ATU_LIMIT			0x914
> @@ -81,7 +81,7 @@
>  #define PCIE_ATU_UPPER_TARGET		0x91C
>  
>  #define PCIE_MISC_CONTROL_1_OFF		0x8BC
> -#define PCIE_DBI_RO_WR_EN		(0x1 << 0)
> +#define PCIE_DBI_RO_WR_EN		BIT(0)
>  
>  /*
>   * iATU Unroll-specific register definitions
> @@ -108,7 +108,7 @@
>  		((region) << 9)
>  
>  #define PCIE_GET_ATU_INB_UNR_REG_OFFSET(region) \
> -		(((region) << 9) | (0x1 << 8))
> +		(((region) << 9) | BIT(8))
>  
>  #define MAX_MSI_IRQS			256
>  #define MAX_MSI_IRQS_PER_CTRL		32
> 

Regards,

Gustavo