linux-kernel - Re: [PATCH] RISC-V: defconfig: Enable Generic PCIE by default

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <mhng-ceba7c1a-7334-4869-a7d4-2326b59f82b5@palmer-si-x1c4>
Date:   Wed, 26 Dec 2018 08:52:48 -0800 (PST)
From:   Palmer Dabbelt <palmer@...ive.com>
To:     Paul Walmsley <paul.walmsley@...ive.com>
CC:     Alistair Francis <Alistair.Francis@....com>,
        Paul Walmsley <paul.walmsley@...ive.com>,
        linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject:     Re: [PATCH] RISC-V: defconfig: Enable Generic PCIE by default

On Fri, 21 Dec 2018 11:27:39 PST (-0800), Paul Walmsley wrote:
>
> On Fri, 21 Dec 2018, Alistair Francis wrote:
>
>> When the MicroSemi driver does eventually go upstream this will
>> probably have to be discussed though as either the config or device
>> tree will need to be edited to ensure only one PCIe device is present.
>
> The right way to do that is to have two separate DT files: one for the
> HiFive-U board alone; the other for the HiFive-U plus the expansion board
> combo.  There shouldn't be any problems with keeping both drivers enabled
> in the defconfig.

We actually need at least three:

* One for the HiFive Unleashed
* One for the HiFive Unleashed, when attached to the Micro Semi expansion 
  board.
* One for the HiFive Unleashed, when attached to a VC707.

We may end up needing additional device trees for the newer Xilinx boards, 
depending on if it's possible to probe for that 32-bit DMA limit on the VC707 
or not.  Then, of course, we'll need an image-specific device tree whenever we 
put an accelerator on the FPGA.

Ideally we'd have a discoverable bus, but that's going to be a bit of a way 
out.  For now we'll have to get by with different device trees, but that should 
get significantly easier when we get a proper bootloader working.