linux-kernel - RE: [PATCH V6 2/2] mmc: tegra: HW Command Queue Support for Tegra SDMMC

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Message-ID: <BN7PR12MB2836645A118593A969ABA5AEC2B70@BN7PR12MB2836.namprd12.prod.outlook.com>
Date:   Fri, 28 Dec 2018 20:16:15 +0000
From:   Sowjanya Komatineni <skomatineni@...dia.com>
To:     Adrian Hunter <adrian.hunter@...el.com>,
        "ulf.hansson@...aro.org" <ulf.hansson@...aro.org>,
        Mikko Perttunen <mperttunen@...dia.com>
CC:     "thierry.reding@...il.com" <thierry.reding@...il.com>,
        Jonathan Hunter <jonathanh@...dia.com>,
        "linux-tegra@...r.kernel.org" <linux-tegra@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-mmc@...r.kernel.org" <linux-mmc@...r.kernel.org>
Subject: RE: [PATCH V6 2/2] mmc: tegra: HW Command Queue Support for Tegra
 SDMMC

Hi Adrian

>> This patch adds HW Command Queue for supported Tegra SDMMC 
>> controllers.
>> 
>> Tegra SDHCI with Quirk SDHCI_QUIRK2_BROKEN_64_BIT_DMA disables the use 
>> of 64_BIT DMA to disable 64-bit addressing mode access to the system 
>> memory and sdhci_cqe_enable using flag SDHCI_USE_64_BIT_DMA for 
>> ADMA32/ADMA2 Vs ADMA64/ADMA3 DMA selection.
>> 
>> CQE need to use ADMA3 as it need to fetch task descriptor along with 
>> transfer descriptor, so this patch forces DMA Select to be
>> ADMA3 for CQE.

> I don't understand why you use the term "ADMA3" since it is not CQE terminology, can be 32-bit or 64-bit, and, from the driver point of view, has quite different requirements from CQE.
> 
> It seems you are saying that Tegra supports only 32-bit DMA but must select 64-bit DMA for CQE?  Can you clarify this a bit?
> 

As per Host Spec, When Host Version 4 is enabled, DMA_SELECT options supported are
00: SDMA
01: Not Used
10: ADMA2
11: ADMA2 or ADMA3

When Host Version 4 is disabled, DMA_SELECT options supported are
00: SDMA
01: Not Used
10: 32-Bit addressing ADMA2
11: 64-Bit addressing ADMA2

Version 4 is enabled for CQE and need to use ADMA3 DMA Select. ADMA3 enables host to program multiple ADMA2 operations.
CQE need to fetch both task descriptor and transfer descriptor and should use ADMA3.
ADMA3 is supported with both 32-bit and 64-bit addressing modes. 
SDHCI driver has DMA select options defined as per Host versions below 4 and using ADMA32, ADMA64 which are equivalent to ADMA2 and ADMA3 for Host V4.
If using same ADMA64 is adding confusion, probably I can add define ADMA3_CQE with same b'11 to avoid confusion. Please let me know.

>> 
>> Tegra SDMMC Host design prevents write access to BLOCK_COUNT registers 
>> when CQE is enabled to prevent SW from updating block size during 
>> Command Queue mode.
>> 
>> Signed-off-by: Sowjanya Komatineni <skomatineni@...dia.com>
>> ---
>>  drivers/mmc/host/Kconfig       |   1 +
>>  drivers/mmc/host/sdhci-tegra.c | 107 ++++++++++++++++++++++++++++++++++++++++-
>>  drivers/mmc/host/sdhci.c       |   6 ++-
>>  3 files changed, 112 insertions(+), 2 deletions(-)

Thanks & Regards,
Sowjanya