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Message-ID: <20181231172654.GB14092@amd>
Date: Mon, 31 Dec 2018 18:26:54 +0100
From: Pavel Machek <pavel@....cz>
To: David Wang <davidwang@...oxin.com>
Cc: rjw@...ysocki.net, mingo@...hat.com, len.brown@...el.com,
tglx@...utronix.de, hpa@...or.com, x86@...nel.org,
linux-pm@...nel.org, linux-kernel@...r.kernel.org,
brucechang@...-alliance.com, cooperyan@...oxin.com,
qiyuanwang@...oxin.com, timguo@...oxin.com
Subject: Re: [PATCH v3] Optimize C3 entry on Centaur CPUs
On Thu 2018-12-27 16:41:50, David Wang wrote:
> For new Centaur CPUs the ucode will take care of the preservation of cache coherence
> between CPU cores in C-states regardless of how deep the C-states are. So, it is not
> necessary to flush the caches in software befor entering C3. And this useless operation
> will cause performance drop for the cores which share some caches with the idling core.
>
> Signed-off-by: David Wang <davidwang@...oxin.com>
> Reviewed-by: Thomas Gleixner <tglx@...utronix.de>
Acked-by: Pavel Machek <pavel@....cz>
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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