| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <1546244693-34633-3-git-send-email-ley.foon.tan@intel.com>
Date: Mon, 31 Dec 2018 16:24:53 +0800
From: Ley Foon Tan <ley.foon.tan@...el.com>
To: Bjorn Helgaas <bhelgaas@...gle.com>
Cc: linux-kernel@...r.kernel.org, linux-pci@...r.kernel.org,
lftan.linux@...il.com, Ley Foon Tan <ley.foon.tan@...el.com>
Subject: [PATCH v2 2/2] Documentation: dt-bindings: pci: altera: Add altr,pcie-root-port-2.0
Add support for altr,pcie-root-port-2.0.
Signed-off-by: Ley Foon Tan <ley.foon.tan@...el.com>
---
.../devicetree/bindings/pci/altera-pcie.txt | 4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/altera-pcie.txt b/Documentation/devicetree/bindings/pci/altera-pcie.txt
index 6c396f1..816b244 100644
--- a/Documentation/devicetree/bindings/pci/altera-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/altera-pcie.txt
@@ -1,11 +1,13 @@
* Altera PCIe controller
Required properties:
-- compatible : should contain "altr,pcie-root-port-1.0"
+- compatible : should contain "altr,pcie-root-port-1.0" or "altr,pcie-root-port-2.0"
- reg: a list of physical base address and length for TXS and CRA.
+ For "altr,pcie-root-port-2.0", additional HIP base address and length.
- reg-names: must include the following entries:
"Txs": TX slave port region
"Cra": Control register access region
+ "Hip": Hard IP region (if "altr,pcie-root-port-2.0")
- interrupts: specifies the interrupt source of the parent interrupt
controller. The format of the interrupt specifier depends
on the parent interrupt controller.
--
1.7.1
Powered by blists - more mailing lists