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Date:   Wed, 2 Jan 2019 09:33:01 +0000
From:   Gustavo Pimentel <gustavo.pimentel@...opsys.com>
To:     Andrey Smirnov <andrew.smirnov@...il.com>,
        "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>
CC:     Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        Fabio Estevam <fabio.estevam@....com>,
        Chris Healy <cphealy@...il.com>,
        Lucas Stach <l.stach@...gutronix.de>,
        Leonard Crestez <leonard.crestez@....com>,
        "A.s. Dong" <aisheng.dong@....com>,
        Richard Zhu <hongxing.zhu@....com>,
        "linux-imx@....com" <linux-imx@....com>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 07/21] PCI: designware: Make use of IS_ALIGNED()

Hi,

On 21/12/2018 07:27, Andrey Smirnov wrote:
> Make the intent a bit more clear as well as get rid of explicit
> arithmetic by using IS_ALIGNED() to determine if "addr" is aligned to
> "size". No functional change intended.
> 
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@....com>
> Cc: Bjorn Helgaas <bhelgaas@...gle.com>
> Cc: Fabio Estevam <fabio.estevam@....com>
> Cc: Chris Healy <cphealy@...il.com>
> Cc: Lucas Stach <l.stach@...gutronix.de>
> Cc: Leonard Crestez <leonard.crestez@....com>
> Cc: "A.s. Dong" <aisheng.dong@....com>
> Cc: Richard Zhu <hongxing.zhu@....com>
> Cc: linux-imx@....com
> Cc: linux-arm-kernel@...ts.infradead.org
> Cc: linux-kernel@...r.kernel.org
> Cc: linux-pci@...r.kernel.org
> Signed-off-by: Andrey Smirnov <andrew.smirnov@...il.com>
> ---
>  drivers/pci/controller/dwc/pcie-designware.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index 93ef8c31fb39..67236379c61a 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -22,7 +22,7 @@
>  
>  int dw_pcie_read(void __iomem *addr, int size, u32 *val)
>  {
> -	if ((uintptr_t)addr & (size - 1)) {
> +	if (!IS_ALIGNED((uintptr_t)addr, size)) {
>  		*val = 0;
>  		return PCIBIOS_BAD_REGISTER_NUMBER;
>  	}
> @@ -43,7 +43,7 @@ int dw_pcie_read(void __iomem *addr, int size, u32 *val)
>  
>  int dw_pcie_write(void __iomem *addr, int size, u32 val)
>  {
> -	if ((uintptr_t)addr & (size - 1))
> +	if (!IS_ALIGNED((uintptr_t)addr, size))
>  		return PCIBIOS_BAD_REGISTER_NUMBER;
>  
>  	if (size == 4)
> 

Sounds good.

Acked-by: Gustavo Pimentel <gustavo.pimentel@...opsys.com>

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