linux-kernel - Re: [PATCH 2/3] qcom: spmi-gpio: add support for hierarchical IRQ chip

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Message-ID: <20190105125115.GA2647@basecamp>
Date:   Sat, 5 Jan 2019 07:51:15 -0500
From:   Brian Masney <masneyb@...tation.org>
To:     Stephen Boyd <sboyd@...nel.org>
Cc:     andy.gross@...aro.org, bjorn.andersson@...aro.org,
        linus.walleij@...aro.org, marc.zyngier@....com,
        shawnguo@...nel.org, dianders@...omium.org,
        linux-gpio@...r.kernel.org, nicolas.dechesne@...aro.org,
        niklas.cassel@...aro.org, david.brown@...aro.org,
        robh+dt@...nel.org, mark.rutland@....com, thierry.reding@...il.com,
        linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
        devicetree@...r.kernel.org
Subject: Re: [PATCH 2/3] qcom: spmi-gpio: add support for hierarchical IRQ
 chip

On Sat, Jan 05, 2019 at 07:08:44AM -0500, Brian Masney wrote:
> > I also seem to recall that GPIO numbering starts from 1 instead of
> > 0, so please keep that in mind.
> 
> I'm using the pinctrl numbering, which is zero based.
> 
> / # head /sys/kernel/debug/pinctrl/fc4cf000.spmi\:pm8941@0\:gpios@...0/pins 
> registered pins: 36
> pin 0 (gpio1) 
> pin 1 (gpio2) 
> pin 2 (gpio3) 
> pin 3 (gpio4) 
> pin 4 (gpio5) 
> pin 5 (gpio6) 
> pin 6 (gpio7) 
> pin 7 (gpio8) 
> pin 8 (gpio9) 

After more thought: the pin numbering from pinctrl is an implementation
detail that device tree should not be aware of. This needs to be the
GPIO pin number. I'll correct this in v2.

Brian