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Message-ID: <1546857399-2926-1-git-send-email-shirish.s@amd.com>
Date: Mon, 7 Jan 2019 10:37:07 +0000
From: "S, Shirish" <Shirish.S@....com>
To: unlisted-recipients:; (no To-header on input)
CC: Thomas Gleixner <tglx@...utronix.de>,
Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
"H . Peter Anvin" <hpa@...or.com>,
"maintainer : X86 ARCHITECTURE" <x86@...nel.org>,
Tony Luck <tony.luck@...el.com>,
Vishal Verma <vishal.l.verma@...el.com>,
"open list : X86 ARCHITECTURE" <linux-kernel@...r.kernel.org>,
"S, Shirish" <Shirish.S@....com>
Subject: [PATCH 0/2] x86/mce/amd: apply missing quirks for family 15 models
This patch series applies to family 15 CPU's of AMD platforms,
so as to address a consistent warning of
"[Firmware Bug]: cpu 0, invalid threshold interrupt offset"
at every boot and upon completiong of successful S3 cycle,
due to a missing quirk, which was not extended to newer models
and also not applied in resume path.
Shirish S (2):
x86/mce/amd: Extend "Disable error thresholding bank 4" to more models
x86/mce/amd: Ensure quirks are applied in resume path as well
arch/x86/kernel/cpu/mce/amd.c | 34 ++++++++++++++++++++++++++++++++++
arch/x86/kernel/cpu/mce/core.c | 2 +-
2 files changed, 35 insertions(+), 1 deletion(-)
--
2.7.4
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