| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <1546956464-48825-1-git-send-email-julien.thierry@arm.com>
Date: Tue, 8 Jan 2019 14:07:18 +0000
From: Julien Thierry <julien.thierry@....com>
To: linux-arm-kernel@...ts.infradead.org
Cc: linux-kernel@...r.kernel.org, daniel.thompson@...aro.org,
joel@...lfernandes.org, marc.zyngier@....com,
christoffer.dall@....com, james.morse@....com,
catalin.marinas@....com, will.deacon@....com, mark.rutland@....com,
Julien Thierry <julien.thierry@....com>
Subject: [PATCH v8 00/26] arm64: provide pseudo NMI with GICv3
Hi,
This series is a continuation of the work started by Daniel [1]. The goal
is to use GICv3 interrupt priorities to simulate an NMI.
The patches depend on the core API for NMIs patches [2]. Both series can
be found on this branch:
git clone http://linux-arm.org/linux-jt.git -b v4.20-pseudo-nmi
To achieve this, set two priorities, one for standard interrupts and
another, higher priority, for NMIs. Whenever we want to disable interrupts,
we mask the standard priority instead so NMIs can still be raised. Some
corner cases though still require to actually mask all interrupts
effectively disabling the NMI.
Daniel Thompson ran some benchmarks [3] on a previous version showing a
small (<1%) performance drop when using interrupt priorities on Cortex-A53
and GIC-500.
Currently, only PPIs and SPIs can be set as NMIs. IPIs being currently
hardcoded IRQ numbers, there isn't a generic interface to set SGIs as NMI
for now. LPIs being controlled by the ITS cannot be delivered as NMI.
When an NMI is active on a CPU, no other NMI can be triggered on the CPU.
Requirements to use this:
- Have GICv3
- SCR_EL3.FIQ is set to 1 when linux runs or have single security state
- Select Kernel Feature -> Support for NMI-like interrupts
- Provide "enable_pseudo_nmi" on the kernel command line
* Patch 1 fixes an existing issue with current NMI contexts in arm64
* Patches 2 and 3 are just a bit of cleanup
* Patch 4 introduces a CPU feature to check if priority masking should be
used
* Patches 5 and 6 add the support for priority masking in GICv3 driver
* Patches 7 to 13 add the support for priority masking the arch/arm64
code
* Patches 14 and 15 allow us to apply alternatives earlier in the boot
process
* Patches 16 to 18 starts the PMR masking on cpu startup and provides
primitives for arm64 GICv3 driver to perform priority masking
* Patches 19 to 22 Add support for pseudo-NMIs in GICv3 driver
* Patches 23 to 25 Add support for receiving NMIs in arch/arm64
* Patch 26 adds the build config and command line option to enable
pseudo-NMIs
Changes since v7[4]:
* Rebase on v5.0-rc1
* Move default arch_nmi_enter/exit definition to fix build issues
* Override flags to preserve accross EFI services calls
[1] http://www.spinics.net/lists/arm-kernel/msg525077.html
[2] https://lkml.org/lkml/2018/11/12/2113
[3] https://lkml.org/lkml/2018/7/20/803
[4] https://www.spinics.net/lists/arm-kernel/msg695086.html
Cheers,
Julien
-->
Daniel Thompson (1):
arm64: alternative: Apply alternatives early in boot process
Julien Thierry (25):
arm64: Fix HCR.TGE status for NMI contexts
arm64: Remove unused daif related functions/macros
arm64: cpufeature: Set SYSREG_GIC_CPUIF as a boot system feature
arm64: cpufeature: Add cpufeature for IRQ priority masking
arm/arm64: gic-v3: Add PMR and RPR accessors
irqchip/gic-v3: Switch to PMR masking before calling IRQ handler
arm64: ptrace: Provide definitions for PMR values
arm64: Make PMR part of task context
arm64: Unmask PMR before going idle
arm64: kvm: Unmask PMR before entering guest
efi: Let architectures decide the flags that should be saved/restored
arm64: irqflags: Use ICC_PMR_EL1 for interrupt masking
arm64: daifflags: Include PMR in daifflags restore operations
arm64: alternative: Allow alternative status checking per cpufeature
irqchip/gic-v3: Factor group0 detection into functions
arm64: Switch to PMR masking when starting CPUs
arm64: gic-v3: Implement arch support for priority masking
irqchip/gic-v3: Detect if GIC can support pseudo-NMIs
irqchip/gic-v3: Handle pseudo-NMIs
irqchip/gic: Add functions to access irq priorities
irqchip/gic-v3: Allow interrupts to be set as pseudo-NMI
arm64: Handle serror in NMI context
arm64: Skip preemption when exiting an NMI
arm64: Skip irqflags tracing for NMI in IRQs disabled context
arm64: Enable the support of pseudo-NMIs
Documentation/admin-guide/kernel-parameters.txt | 6 +
Documentation/arm64/booting.txt | 5 +
arch/arm/include/asm/arch_gicv3.h | 33 ++++
arch/arm64/Kconfig | 14 ++
arch/arm64/include/asm/alternative.h | 4 +-
arch/arm64/include/asm/arch_gicv3.h | 32 +++
arch/arm64/include/asm/assembler.h | 10 +-
arch/arm64/include/asm/cpucaps.h | 3 +-
arch/arm64/include/asm/cpufeature.h | 10 +
arch/arm64/include/asm/daifflags.h | 41 ++--
arch/arm64/include/asm/efi.h | 11 ++
arch/arm64/include/asm/hardirq.h | 28 +++
arch/arm64/include/asm/irqflags.h | 123 +++++++++---
arch/arm64/include/asm/kvm_host.h | 12 ++
arch/arm64/include/asm/processor.h | 3 +
arch/arm64/include/asm/ptrace.h | 26 ++-
arch/arm64/kernel/alternative.c | 60 +++++-
arch/arm64/kernel/asm-offsets.c | 1 +
arch/arm64/kernel/cpufeature.c | 42 +++-
arch/arm64/kernel/entry.S | 43 ++++
arch/arm64/kernel/irq.c | 3 +
arch/arm64/kernel/process.c | 51 +++++
arch/arm64/kernel/smp.c | 33 ++++
arch/arm64/kernel/traps.c | 8 +-
arch/arm64/kvm/hyp/switch.c | 16 ++
arch/arm64/mm/proc.S | 11 --
drivers/firmware/efi/runtime-wrappers.c | 17 +-
drivers/irqchip/irq-gic-common.c | 10 +
drivers/irqchip/irq-gic-common.h | 2 +
drivers/irqchip/irq-gic-v3.c | 252 +++++++++++++++++++++---
include/linux/efi.h | 5 +-
include/linux/hardirq.h | 7 +
32 files changed, 807 insertions(+), 115 deletions(-)
--
1.9.1
Powered by blists - more mailing lists