linux-kernel - [tip:perf/urgent] tools headers x86: Sync asm/cpufeatures.h copy with the kernel sources

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Message-ID: <tip-aonti3bu9rhnqe5hlawbidcp@git.kernel.org>
Date:   Tue, 8 Jan 2019 07:42:58 -0800
From:   tip-bot for Arnaldo Carvalho de Melo <tipbot@...or.com>
To:     linux-tip-commits@...r.kernel.org
Cc:     robert.hu@...ux.intel.com, namhyung@...nel.org, tglx@...utronix.de,
        Thomas.Lendacky@....com, adrian.hunter@...el.com,
        pbonzini@...hat.com, jolsa@...nel.org,
        linux-kernel@...r.kernel.org, acme@...hat.com, hpa@...or.com,
        mingo@...nel.org
Subject: [tip:perf/urgent] tools headers x86: Sync asm/cpufeatures.h copy
 with the kernel sources

Commit-ID:  86c22ab7227f59169f64275875c97ef495668b77
Gitweb:     https://git.kernel.org/tip/86c22ab7227f59169f64275875c97ef495668b77
Author:     Arnaldo Carvalho de Melo <acme@...hat.com>
AuthorDate: Fri, 4 Jan 2019 12:13:34 -0300
Committer:  Arnaldo Carvalho de Melo <acme@...hat.com>
CommitDate: Fri, 4 Jan 2019 12:54:49 -0300

tools headers x86: Sync asm/cpufeatures.h copy with the kernel sources

To get the changes from:

  a0aea130afeb ("KVM: x86: Add CPUID support for new instruction WBNOINVD")
  20c3a2c33e9f ("x86/speculation: Add support for STIBP always-on preferred mode")

Cc: Adrian Hunter <adrian.hunter@...el.com>
Cc: Jiri Olsa <jolsa@...nel.org>
Cc: Namhyung Kim <namhyung@...nel.org>
Cc: Paolo Bonzini <pbonzini@...hat.com>
Cc: Robert Hoo <robert.hu@...ux.intel.com>
Cc: Thomas Gleixner <tglx@...utronix.de>
Cc: Thomas Lendacky <Thomas.Lendacky@....com>
Link: https://lkml.kernel.org/n/tip-aonti3bu9rhnqe5hlawbidcp@git.kernel.org
Signed-off-by: Arnaldo Carvalho de Melo <acme@...hat.com>
---
 tools/arch/x86/include/asm/cpufeatures.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/tools/arch/x86/include/asm/cpufeatures.h b/tools/arch/x86/include/asm/cpufeatures.h
index 28c4a502b419..6d6122524711 100644
--- a/tools/arch/x86/include/asm/cpufeatures.h
+++ b/tools/arch/x86/include/asm/cpufeatures.h
@@ -281,9 +281,11 @@
 #define X86_FEATURE_CLZERO		(13*32+ 0) /* CLZERO instruction */
 #define X86_FEATURE_IRPERF		(13*32+ 1) /* Instructions Retired Count */
 #define X86_FEATURE_XSAVEERPTR		(13*32+ 2) /* Always save/restore FP error pointers */
+#define X86_FEATURE_WBNOINVD		(13*32+ 9) /* WBNOINVD instruction */
 #define X86_FEATURE_AMD_IBPB		(13*32+12) /* "" Indirect Branch Prediction Barrier */
 #define X86_FEATURE_AMD_IBRS		(13*32+14) /* "" Indirect Branch Restricted Speculation */
 #define X86_FEATURE_AMD_STIBP		(13*32+15) /* "" Single Thread Indirect Branch Predictors */
+#define X86_FEATURE_AMD_STIBP_ALWAYS_ON	(13*32+17) /* "" Single Thread Indirect Branch Predictors always-on preferred */
 #define X86_FEATURE_AMD_SSBD		(13*32+24) /* "" Speculative Store Bypass Disable */
 #define X86_FEATURE_VIRT_SSBD		(13*32+25) /* Virtualized Speculative Store Bypass Disable */
 #define X86_FEATURE_AMD_SSB_NO		(13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */