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Date:   Wed, 9 Jan 2019 22:14:32 +0000
From:   Chris Brandt <>
To:     Sergei Shtylyov <>,
        Geert Uytterhoeven <>
CC:     Mason Yang <>,
        Mark Brown <>,
        Marek Vasut <>,
        Linux Kernel Mailing List <>,
        linux-spi <>,
        Boris Brezillon <>,
        Linux-Renesas <>,
        Geert Uytterhoeven <>,
        "" <>,
        Simon Horman <>,
        "" <>
Subject: RE: [PATCH v5 1/2] spi: Add Renesas R-Car Gen3 RPC-IF SPI controller

On Wednesday, January 09, 2019, Sergei Shtylyov wrote:
> > IIRC, this hardware block is also used on RZ/A, which is 32-bit.
>   I'm not seeing it in the "RZ/A1H Group, RZ/A1M Group User’s Manual:
> Hardware"
> Rev 3.00. What SoC did you have in mind?

For the RZ/A series (and RZ/T series), it is called the
"SPI Multi I/O Bus Controller" (Chapter 17)

I have no idea why it has a different name for the same hardware (and
the same pages in the manual).

The HW version in RZ/A1 does not have HyperRAM.

But the HW version in RZ/A2 is the same as what is in R-Car Gen3.


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