lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <20190109152749.GA6890@ziepe.ca>
Date:   Wed, 9 Jan 2019 08:27:49 -0700
From:   Jason Gunthorpe <jgg@...pe.ca>
To:     Benjamin Herrenschmidt <benh@...nel.crashing.org>
Cc:     David Gibson <david@...son.dropbear.id.au>,
        Leon Romanovsky <leon@...nel.org>, davem@...emloft.net,
        saeedm@...lanox.com, ogerlitz@...lanox.com, tariqt@...lanox.com,
        bhelgaas@...gle.com, linux-kernel@...r.kernel.org,
        linuxppc-dev@...ts.ozlabs.org, netdev@...r.kernel.org,
        alex.williamson@...hat.com, linux-pci@...r.kernel.org,
        linux-rdma@...r.kernel.org, sbest@...hat.com, paulus@...ba.org,
        Alexey Kardashevskiy <aik@....ibm.com>
Subject: Re: [PATCH] PCI: Add no-D3 quirk for Mellanox ConnectX-[45]

On Wed, Jan 09, 2019 at 04:09:02PM +1100, Benjamin Herrenschmidt wrote:

> > POWER 8 firmware is good? If the link does eventually come back, is
> > the POWER8's D3 resumption timeout long enough?
> > 
> > If this doesn't lead to an obvious conclusion you'll probably need to
> > connect to IBM's Mellanox support team to get more information from
> > the card side.
> 
> We are IBM :-) So far, it seems to be that the card is doing something
> not quite right, but we don't know what. We might need to engage
> Mellanox themselves.

Sorry, it was unclear, I ment the support team for IBM inside Mellanox
..

There might be internal debugging available that can show if the card
is detecting the beacon, how far it gets in renegotiation, etc.

>From all the mails it really has the feel of a PCI-E interop problem between
these two specific chips..

Jason

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ