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Message-ID: <3d3f3726-0eef-00c5-1444-a4112af683ac@gmail.com>
Date: Wed, 9 Jan 2019 17:55:17 +0100
From: Matthias Brugger <matthias.bgg@...il.com>
To: chunhui dai <chunhui.dai@...iatek.com>,
--to=Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>, CK Hu <ck.hu@...iatek.com>
Cc: Philipp Zabel <p.zabel@...gutronix.de>,
David Airlie <airlied@...ux.ie>,
Sean Wang <sean.wang@...iatek.com>,
Ryder Lee <ryder.lee@...iatek.com>,
Colin Ian King <colin.king@...onical.com>,
linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-mediatek@...ts.infradead.org,
dri-devel@...ts.freedesktop.org, srv_heupstream@...iatek.com,
bibby.hsieh@...iatek.com, jamesjj.liao@...iatek.com,
jitao.shi@...iatek.com
Subject: Re: [PATCH 1/9] drm/mediatek: recalculate hdmi phy clock of MT2701 by
querying hardware
On 04/01/2019 08:03, chunhui dai wrote:
> Recalculate the rate of this clock, by querying hardware.
>
> Signed-off-by: chunhui dai <chunhui.dai@...iatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_hdmi_phy.c | 7 ++--
> drivers/gpu/drm/mediatek/mtk_hdmi_phy.h | 3 +-
> drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 49 ++++++++++++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 8 +++++
> 4 files changed, 61 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
> index 4ef9c57..79e737d 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.c
> @@ -29,12 +29,11 @@ long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
> return rate;
> }
>
> -unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
> - unsigned long parent_rate)
> +u32 mtk_hdmi_phy_read(struct mtk_hdmi_phy *hdmi_phy, u32 offset)
> {
> - struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
> + void __iomem *reg = hdmi_phy->regs + offset;
>
> - return hdmi_phy->pll_rate;
> + return readl(reg);
> }
>
> void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
> diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h
> index f39b1fc..fdad8b1 100644
> --- a/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h
> +++ b/drivers/gpu/drm/mediatek/mtk_hdmi_phy.h
> @@ -41,6 +41,7 @@ struct mtk_hdmi_phy {
> unsigned int ibias_up;
> };
>
> +u32 mtk_hdmi_phy_read(struct mtk_hdmi_phy *hdmi_phy, u32 offset);
> void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
> u32 bits);
> void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
> @@ -50,8 +51,6 @@ void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
> struct mtk_hdmi_phy *to_mtk_hdmi_phy(struct clk_hw *hw);
> long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
> unsigned long *parent_rate);
> -unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
> - unsigned long parent_rate);
>
> extern struct platform_driver mtk_hdmi_phy_driver;
> extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf;
> diff --git a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
> index fcc42dc..b5ed6b7 100644
> --- a/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
> +++ b/drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c
> @@ -153,6 +153,55 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
> RG_HDMITX_DRV_IBIAS_MASK);
> return 0;
> }
> +static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
> + unsigned long out_rate, val;
> +
> + val = (mtk_hdmi_phy_read(hdmi_phy, HDMI_CON6)
> + & RG_HTPLL_PREDIV_MASK) >> RG_HTPLL_PREDIV;
> + switch (val) {
> + case 0x00:
> + out_rate = parent_rate;
> + break;
> + case 0x01:
> + out_rate = parent_rate / 2;
> + break;
> + default:
> + out_rate = parent_rate / 4;
> + break;
> + }
> +
> + val = (mtk_hdmi_phy_read(hdmi_phy, HDMI_CON6)
> + & RG_HTPLL_FBKDIV_MASK) >> RG_HTPLL_FBKDIV;
> + out_rate = out_rate * (val + 1) * 2;
> + val = (mtk_hdmi_phy_read(hdmi_phy, HDMI_CON2)
> + & RG_HDMITX_TX_POSDIV_MASK) >> RG_HDMITX_TX_POSDIV;
> + switch (val) {
> + case 0x00:
> + out_rate = out_rate;
> + break;
> + case 0x01:
> + out_rate = out_rate / 2;
> + break;
> + case 0x02:
> + out_rate = out_rate / 4;
> + break;
> + case 0x03:
> + out_rate = out_rate / 8;
> + break;
> + default:
> + break;
> + }
> +
> + if (mtk_hdmi_phy_read(hdmi_phy, HDMI_CON2) & RG_HDMITX_EN_TX_POSDIV)
Is this path time critical? You are reading the same register twice instead of
saving the read in a local varibale.
Regards,
Matthias
> + out_rate = out_rate / 5;
> +
> + hdmi_phy->pll_rate = out_rate;
> +
> + return hdmi_phy->pll_rate;
> +}
>
> static const struct clk_ops mtk_hdmi_phy_pll_ops = {
> .prepare = mtk_hdmi_pll_prepare,
> diff --git a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
> index ed5916b..cb23c1e 100644
> --- a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
> +++ b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
> @@ -285,6 +285,14 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
> return 0;
> }
>
> +static unsigned long mtk_hdmi_pll_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
> +
> + return hdmi_phy->pll_rate;
> +}
> +
> static const struct clk_ops mtk_hdmi_phy_pll_ops = {
> .prepare = mtk_hdmi_pll_prepare,
> .unprepare = mtk_hdmi_pll_unprepare,
>
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