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Message-ID: <154706034090.15366.11081837995313995010@swboyd.mtv.corp.google.com>
Date:   Wed, 09 Jan 2019 10:59:00 -0800
From:   Stephen Boyd <sboyd@...nel.org>
To:     Jeffrey Hugo <jhugo@...eaurora.org>, mturquette@...libre.com
Cc:     bjorn.andersson@...aro.org, andy.gross@...aro.org,
        david.brown@...aro.org, linux-arm-msm@...r.kernel.org,
        linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
        kishon@...com, robh+dt@...nel.org, mark.rutland@....com,
        devicetree@...r.kernel.org, gregkh@...uxfoundation.org,
        balbi@...nel.org, linux-usb@...r.kernel.org,
        Jeffrey Hugo <jhugo@...eaurora.org>
Subject: Re: [PATCH v1 2/6] clk: qcom: Skip halt checks on gcc_usb3_phy_pipe_clk for 8998

Quoting Jeffrey Hugo (2019-01-04 08:50:15)
> The gcc_usb3_phy_pipe_clk is generated by the phy, but is also used by
> the phy during init.  The clock needs to be enabled during the init
> sequence, but may not be fully active until after the init sequence is
> complete.  This causes a catch-22 if the clock status is checked during
> enable.  As a result, skip the checks to avoid the troubling situation.

I will ask again, is anyone going to fix this in the phy driver? In
theory it isn't needed if the phy driver can do things differently, but
last time I checked I was told that the phy team said it had to be done
this way.

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