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Message-ID: <20190110160054.GD17621@zn.tnic>
Date: Thu, 10 Jan 2019 17:00:54 +0100
From: Borislav Petkov <bp@...en8.de>
To: Paul Menzel <pmenzel@...gen.mpg.de>
Cc: Thomas Lendacky <Thomas.Lendacky@....com>,
Thomas Gleixner <tglx@...utronix.de>,
Jiri Kosina <jikos@...nel.org>,
"x86@...nel.org" <x86@...nel.org>,
LKML <linux-kernel@...r.kernel.org>,
Tim Chen <tim.c.chen@...ux.intel.com>
Subject: Re: General protection fault in `switch_mm_irqs_off()`
On Thu, Jan 10, 2019 at 02:57:40PM +0100, Paul Menzel wrote:
> Thank you very much. Indeed, the machine does not crash. I used Linus’
> master branch for testing, and applied your patch on top. Please find
> the full log attached.
> 80.649: [ 3.197107] Spectre V2 : spectre_v2_user_select_mitigation: set X86_FEATURE_USE_IBPB
This is amazing.
Ok, next diff, same exercise. Thx.
---
diff --git a/arch/x86/include/asm/nospec-branch.h b/arch/x86/include/asm/nospec-branch.h
index dad12b767ba0..528ef8336f5f 100644
--- a/arch/x86/include/asm/nospec-branch.h
+++ b/arch/x86/include/asm/nospec-branch.h
@@ -284,6 +284,12 @@ static inline void indirect_branch_prediction_barrier(void)
{
u64 val = PRED_CMD_IBPB;
+ if (WARN_ON(boot_cpu_has(X86_FEATURE_USE_IBPB))) {
+ pr_info("%s: c: %px, array: 0x%x\n",
+ __func__, &boot_cpu_data, boot_cpu_data.x86_capability[7]);
+ return;
+ }
+
alternative_msr_write(MSR_IA32_PRED_CMD, val, X86_FEATURE_USE_IBPB);
}
diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c
index 8654b8b0c848..e818e5abe611 100644
--- a/arch/x86/kernel/cpu/bugs.c
+++ b/arch/x86/kernel/cpu/bugs.c
@@ -371,6 +371,9 @@ spectre_v2_user_select_mitigation(enum spectre_v2_mitigation_cmd v2_cmd)
if (boot_cpu_has(X86_FEATURE_IBPB)) {
setup_force_cpu_cap(X86_FEATURE_USE_IBPB);
+ pr_err("%s: set X86_FEATURE_USE_IBPB, c: %px, array: 0x%x\n",
+ __func__, &boot_cpu_data, boot_cpu_data.x86_capability[7]);
+
switch (cmd) {
case SPECTRE_V2_USER_CMD_FORCE:
case SPECTRE_V2_USER_CMD_PRCTL_IBPB:
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index cb28e98a0659..8566737fa500 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -765,6 +765,9 @@ static void apply_forced_caps(struct cpuinfo_x86 *c)
c->x86_capability[i] &= ~cpu_caps_cleared[i];
c->x86_capability[i] |= cpu_caps_set[i];
}
+
+ if (c == &boot_cpu_data)
+ pr_info("%s: c: %px, array: 0x%x\n", __func__, c, c->x86_capability[7]);
}
static void init_speculation_control(struct cpuinfo_x86 *c)
@@ -778,6 +781,10 @@ static void init_speculation_control(struct cpuinfo_x86 *c)
if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) {
set_cpu_cap(c, X86_FEATURE_IBRS);
set_cpu_cap(c, X86_FEATURE_IBPB);
+
+ pr_info("%s: X86_FEATURE_SPEC_CTRL: c: %px, array: 0x%x, CPUID: 0x%x\n",
+ __func__, c, c->x86_capability[7], cpuid_edx(7));
+
set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
}
@@ -793,9 +800,13 @@ static void init_speculation_control(struct cpuinfo_x86 *c)
set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
}
- if (cpu_has(c, X86_FEATURE_AMD_IBPB))
+ if (cpu_has(c, X86_FEATURE_AMD_IBPB)) {
set_cpu_cap(c, X86_FEATURE_IBPB);
+ pr_info("%s: X86_FEATURE_AMD_IBPB: c: %px, array: 0x%x, CPUID: 0x%x\n",
+ __func__, c, c->x86_capability[7], cpuid_ebx(0x80000008));
+ }
+
if (cpu_has(c, X86_FEATURE_AMD_STIBP)) {
set_cpu_cap(c, X86_FEATURE_STIBP);
set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
--
Regards/Gruss,
Boris.
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