linux-kernel - Re: [PATCH v3 0/6] Static calls

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Message-ID: <207c865e-a92a-1647-b1b0-363010383cc3@zytor.com>
Date:   Sun, 13 Jan 2019 18:40:38 -0800
From:   "H. Peter Anvin" <hpa@...or.com>
To:     Jiri Kosina <jikos@...nel.org>
Cc:     Linus Torvalds <torvalds@...ux-foundation.org>,
        Josh Poimboeuf <jpoimboe@...hat.com>,
        Nadav Amit <namit@...are.com>,
        Andy Lutomirski <luto@...nel.org>,
        Peter Zijlstra <peterz@...radead.org>,
        the arch/x86 maintainers <x86@...nel.org>,
        Linux List Kernel Mailing <linux-kernel@...r.kernel.org>,
        Ard Biesheuvel <ard.biesheuvel@...aro.org>,
        Steven Rostedt <rostedt@...dmis.org>,
        Ingo Molnar <mingo@...nel.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Masami Hiramatsu <mhiramat@...nel.org>,
        Jason Baron <jbaron@...mai.com>,
        David Laight <David.Laight@...lab.com>,
        Borislav Petkov <bp@...en8.de>,
        Julia Cartwright <julia@...com>, Jessica Yu <jeyu@...nel.org>,
        Rasmus Villemoes <linux@...musvillemoes.dk>,
        Edward Cree <ecree@...arflare.com>,
        Daniel Bristot de Oliveira <bristot@...hat.com>
Subject: Re: [PATCH v3 0/6] Static calls

On 1/13/19 6:31 PM, H. Peter Anvin wrote:
> 
> static cpumask_t text_poke_cpumask;
> 
> static void text_poke_sync(void)
> {
> 	smp_wmb();
> 	text_poke_cpumask = cpu_online_mask;
> 	smp_wmb();	/* Should be optional on x86 */
> 	cpumask_clear_cpu(&text_poke_cpumask, smp_processor_id());
> 	on_each_cpu_mask(&text_poke_cpumask, text_poke_sync_cpu, NULL, false);
> 	while (!cpumask_empty(&text_poke_cpumask)) {
> 		cpu_relax();
> 		smp_rmb();
> 	}
> }
> 
> static void text_poke_sync_cpu(void *dummy)
> {
> 	(void)dummy;
> 
> 	smp_rmb();
> 	cpumask_clear_cpu(&poke_bitmask, smp_processor_id());
> 	/*
> 	 * We are guaranteed to return with an IRET, either from the
> 	 * IPI or the #BP handler; this provides serialization.
> 	 */
> }
> 

The invariants here are:

1. The patching routine must set each bit in the cpumask after each event
   that requires synchronization is complete.
2. The bit can be (atomically) cleared on the target CPU only, and only in a
   place that guarantees a synchronizing event (e.g. IRET) before it may
   reaching the poked instruction.
3. At a minimum the IPI handler and #BP handler needs to clear the bit. It
   *is* also possible to clear it in other places, e.g. the NMI handler, if
   necessary as long as condition 2 is satisfied.

	-hpa