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Message-ID: <CACPK8XebHzVAO2TX25N24S0Pgg_0xA=7GN3j0oXhSyD4LmL4=w@mail.gmail.com>
Date: Wed, 16 Jan 2019 10:21:30 +1100
From: Joel Stanley <joel@....id.au>
To: Tomer Maimon <tmaimon77@...il.com>
Cc: Jonathan Cameron <jic23@...nel.org>,
Hartmut Knaack <knaack.h@....de>,
Lars-Peter Clausen <lars@...afoo.de>,
Peter Meerwald-Stadler <pmeerw@...erw.net>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Nancy Yuen <yuenn@...gle.com>,
Patrick Venture <venture@...gle.com>,
Brendan Higgins <brendanhiggins@...gle.com>,
Avi Fishman <avifishman70@...il.com>,
linux-iio@...r.kernel.org,
OpenBMC Maillist <openbmc@...ts.ozlabs.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
devicetree <devicetree@...r.kernel.org>
Subject: Re: [PATCH v2 1/2] dt-binding: iio: add NPCM ADC documentation
On Thu, 10 Jan 2019 at 03:44, Tomer Maimon <tmaimon77@...il.com> wrote:
> +Required Node in the NPCM7xx BMC:
> +An additional register is present in the NPCM7xx SOC which is
> +assumed to be in the same device tree, with and marked as
> +compatible with "nuvoton,npcm750-rst".
Is there a reason you don't include a phandle to the reset node?
I think doing that would make more sense.
> +adc: adc@...0c000 {
> + compatible = "nuvoton,npcm750-adc";
> + reg = <0xf000c000 0x8>;
> + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk NPCM7XX_CLK_ADC>;
> +};
> +
> +rst: rst@...01000 {
> + compatible = "nuvoton,npcm750-rst", "syscon",
> + "simple-mfd";
> + reg = <0xf0801000 0x6C>;
> +};
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