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Message-ID: <87a7k2yx66.fsf@concordia.ellerman.id.au>
Date:   Tue, 15 Jan 2019 22:31:29 +1100
From:   Michael Ellerman <mpe@...erman.id.au>
To:     Will Deacon <will.deacon@....com>,
        "Koenig\, Christian" <Christian.Koenig@....com>
Cc:     Ard Biesheuvel <ard.biesheuvel@...aro.org>,
        Michel Dänzer 
        <michel@...nzer.net>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Carsten Haitzler <Carsten.Haitzler@....com>,
        David Airlie <airlied@...ux.ie>,
        dri-devel <dri-devel@...ts.freedesktop.org>,
        "Huang\, Ray" <Ray.Huang@....com>,
        "Zhang\, Jerry" <Jerry.Zhang@....com>,
        linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
        Bernhard Rosenkränzer 
        <Bernhard.Rosenkranzer@...aro.org>, benh@...nel.crashing.org
Subject: Re: [RFC PATCH] drm/ttm: force cached mappings for system RAM on ARM

Hi Will,

Will Deacon <will.deacon@....com> writes:
> [+ BenH and MPE]
>
> On Mon, Jan 14, 2019 at 07:21:08PM +0000, Koenig, Christian wrote:
>> Am 14.01.19 um 20:13 schrieb Will Deacon:
...
>
>> > The Arm architecture (and others including Power afaiu) doesn't
>> > guarantee coherency when memory is accessed using mismatched cacheability
>> > attributes.
...
>
>> As far as I know Power doesn't really supports un-cached memory at all, 
>> except for a very very old and odd configuration with AGP.
>
> Hopefully Michael/Ben can elaborate here, but I was under the (possibly
> mistaken) impression that mismatched attributes could cause a machine-check
> on Power.

That's what I've always been told, but I can't actually find where it's
documented, I'll keep searching.

But you're right that mixing cached / uncached is not really supported,
and probably results in a machine check or worse.

cheers

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