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Message-ID: <1311521fdd274c08b379cef7252ebd8f@AcuMS.aculab.com>
Date: Tue, 15 Jan 2019 14:33:32 +0000
From: David Laight <David.Laight@...LAB.COM>
To: 'Sebastian Andrzej Siewior' <bigeasy@...utronix.de>
CC: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"x86@...nel.org" <x86@...nel.org>,
Andy Lutomirski <luto@...nel.org>,
"Paolo Bonzini" <pbonzini@...hat.com>,
Radim Krčmář <rkrcmar@...hat.com>,
"kvm@...r.kernel.org" <kvm@...r.kernel.org>,
"Jason A. Donenfeld" <Jason@...c4.com>,
Rik van Riel <riel@...riel.com>,
Dave Hansen <dave.hansen@...ux.intel.com>
Subject: RE: [PATCH v6] x86: load FPU registers on return to userland
From: 'Sebastian Andrzej Siewior'
> Sent: 15 January 2019 13:15
> On 2019-01-15 12:44:53 [+0000], David Laight wrote:
> > Once this is done it might be worth while adding a parameter to
> > kernel_fpu_begin() to request the registers only when they don't
> > need saving.
> > This would benefit code paths where the gains are reasonable but not massive.
>
> So if saving + FPU code is a small win why not do this always?
I was thinking of the case when the cost of the fpu save is greater
than the saving.
This might be true for (say) a crc on a short buffer.
> > The return value from kernel_fpu_begin() ought to indicate which
> > registers are available - none, SSE, SSE2, AVX, AVX512 etc.
> > So code can use an appropriate implementation.
> > (I've not looked to see if this is already the case!)
>
> Either everything is saved or nothing. So if SSE registers are saved
> then AVX512 are, too.
(I know that - I've written fpu save code for AVX).
I was thinking that the return value would depend on what the cpu supports.
In fact, given some talk about big-little cpus it might be worth being
able to ask for a specific register set.
Potentially that could cause a processor switch.
David
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