lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20190115183133.GA12350@lst.de>
Date:   Tue, 15 Jan 2019 19:31:33 +0100
From:   "hch@....de" <hch@....de>
To:     Thomas Hellstrom <thellstrom@...are.com>
Cc:     "hch@....de" <hch@....de>,
        "christian.koenig@....com" <christian.koenig@....com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "yong.zhi@...el.com" <yong.zhi@...el.com>,
        "daniel.vetter@...ll.ch" <daniel.vetter@...ll.ch>,
        "linux-rdma@...r.kernel.org" <linux-rdma@...r.kernel.org>,
        "linux-media@...r.kernel.org" <linux-media@...r.kernel.org>,
        "bingbu.cao@...el.com" <bingbu.cao@...el.com>,
        "jian.xu.zheng@...el.com" <jian.xu.zheng@...el.com>,
        "tian.shu.qiu@...el.com" <tian.shu.qiu@...el.com>,
        "shiraz.saleem@...el.com" <shiraz.saleem@...el.com>,
        "sakari.ailus@...ux.intel.com" <sakari.ailus@...ux.intel.com>,
        "dri-devel@...ts.freedesktop.org" <dri-devel@...ts.freedesktop.org>,
        "jgg@...pe.ca" <jgg@...pe.ca>
Subject: Re: [PATCH] lib/scatterlist: Provide a DMA page iterator

On Tue, Jan 15, 2019 at 06:03:39PM +0000, Thomas Hellstrom wrote:
> In the graphics case, it's probably because it doesn't fit the graphics
> use-cases:
> 
> 1) Memory typically needs to be mappable by another device. (the "dma-
> buf" interface)

And there is nothing preventing dma-buf sharing of these buffers.
Unlike the get_sgtable mess it can actually work reliably on
architectures that have virtually tagged caches and/or don't
guarantee cache coherency with mixed attribute mappings.

> 2) DMA buffers are exported to user-space and is sub-allocated by it.
> Mostly there are no GPU user-space kernel interfaces to sync / flush
> subregions and these syncs may happen on a smaller-than-cache-line
> granularity.

I know of no architectures that can do cache maintainance on a less
than cache line basis.  Either the instructions require you to
specifcy cache lines, or they do sometimes more, sometimes less
intelligent rounding up.

Note that as long dma non-coherent buffers are devices owned it
is up to the device and the user space driver to take care of
coherency, the kernel very much is out of the picture.

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ