linux-kernel - Re: [PATCH v2 1/2] drm/msm: Fix A6XX support for opp-level

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <CAF6AEGsQkKbWRTfT5uJvng7UQmq1rdL8SZrY5Fk205eNujWMCw@mail.gmail.com>
Date:   Wed, 16 Jan 2019 18:32:34 -0500
From:   Rob Clark <robdclark@...il.com>
To:     Douglas Anderson <dianders@...omium.org>
Cc:     Jordan Crouse <jcrouse@...eaurora.org>,
        Bjorn Andersson <bjorn.andersson@...aro.org>,
        Stephen Boyd <swboyd@...omium.org>,
        Rajendra Nayak <rnayak@...eaurora.org>,
        Andy Gross <andy.gross@...aro.org>,
        linux-arm-msm <linux-arm-msm@...r.kernel.org>,
        Viresh Kumar <viresh.kumar@...aro.org>,
        "Kristian H . Kristensen" <hoegsberg@...omium.org>,
        Colin Ian King <colin.king@...onical.com>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        dri-devel <dri-devel@...ts.freedesktop.org>,
        Sharat Masetty <smasetty@...eaurora.org>,
        David Airlie <airlied@...ux.ie>,
        freedreno <freedreno@...ts.freedesktop.org>,
        Mamta Shukla <mamtashukla555@...il.com>,
        Daniel Vetter <daniel@...ll.ch>
Subject: Re: [PATCH v2 1/2] drm/msm: Fix A6XX support for opp-level

s

On Wed, Jan 16, 2019 at 1:46 PM Douglas Anderson <dianders@...omium.org> wrote:
>
> The bindings for Qualcomm opp levels changed after being Acked but
> before landing.  Thus the code in the GPU driver that was relying on
> the old bindings is now broken.
>
> Let's change the code to match the new bindings by adjusting the old
> string 'qcom,level' to the new string 'opp-level'.  See the patch
> ("dt-bindings: opp: Introduce opp-level bindings").
>
> NOTE: we will do additional cleanup to totally remove the string from
> the code and use the new dev_pm_opp_get_level() but we'll do it in a
> future patch.  This will facilitate getting the important code fix in
> sooner without having to deal with cross-maintainer dependencies.
>
> This patch needs to land before the patch ("arm64: dts: sdm845: Add
> gpu and gmu device nodes") since if a tree contains the device tree
> patch but not this one you'll get a crash at bootup.
>
> Fixes: 4b565ca5a2cb ("drm/msm: Add A6XX device support")
> Signed-off-by: Douglas Anderson <dianders@...omium.org>

thanks, I've pulled the first into msm-next and I'll grab the 2nd once
dev_pm_opp_get_level() lands

BR,
-R

> ---
>
> Changes in v2:
> - Split into two patches to facilitate landing.
>
>  drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> index 5beb83d1cf87..ce1b3cc4bf6d 100644
> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
> @@ -944,7 +944,7 @@ static u32 a6xx_gmu_get_arc_level(struct device *dev, unsigned long freq)
>         np = dev_pm_opp_get_of_node(opp);
>
>         if (np) {
> -               of_property_read_u32(np, "qcom,level", &val);
> +               of_property_read_u32(np, "opp-level", &val);
>                 of_node_put(np);
>         }
>
> --
> 2.20.1.97.g81188d93c3-goog
>