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Date: Wed, 16 Jan 2019 09:06:43 -0800
From: Randy Dunlap <rdunlap@...radead.org>
To: Yangtao Li <tiny.windzz@...il.com>, tglx@...utronix.de,
douliyangs@...il.com, marc.zyngier@....com, palmer@...ive.com
Cc: linux-kernel@...r.kernel.org
Subject: Re: [PATCH] irq: convert the code format to BIT()
On 1/16/19 8:03 AM, Yangtao Li wrote:
> Use BIT() to do some clean-up.
>
> Signed-off-by: Yangtao Li <tiny.windzz@...il.com>
> ---
> include/linux/irq.h | 106 ++++++++++++++++++++++----------------------
> 1 file changed, 53 insertions(+), 53 deletions(-)
>
Hi,
>From Documentation/process/submit-checklist.rst, Rule #1:
1) If you use a facility then #include the file that defines/declares
that facility. Don't depend on other header files pulling in ones
that you use.
> diff --git a/include/linux/irq.h b/include/linux/irq.h
> index def2b2aac8b1..66c9801ce108 100644
> --- a/include/linux/irq.h
> +++ b/include/linux/irq.h
> @@ -73,30 +73,30 @@ enum irqchip_irq_state;
> * IRQ_DISABLE_UNLAZY - Disable lazy irq disable
> */
> enum {
> - IRQ_TYPE_NONE = 0x00000000,
> - IRQ_TYPE_EDGE_RISING = 0x00000001,
> - IRQ_TYPE_EDGE_FALLING = 0x00000002,
> + IRQ_TYPE_NONE = 0,
> + IRQ_TYPE_EDGE_RISING = BIT(0),
> + IRQ_TYPE_EDGE_FALLING = BIT(1),
> IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),
> - IRQ_TYPE_LEVEL_HIGH = 0x00000004,
> - IRQ_TYPE_LEVEL_LOW = 0x00000008,
> + IRQ_TYPE_LEVEL_HIGH = BIT(2),
> + IRQ_TYPE_LEVEL_LOW = BIT(3),
> IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),
> - IRQ_TYPE_SENSE_MASK = 0x0000000f,
> + IRQ_TYPE_SENSE_MASK = GENMASK(3,0),
> IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK,
>
> - IRQ_TYPE_PROBE = 0x00000010,
> -
> - IRQ_LEVEL = (1 << 8),
> - IRQ_PER_CPU = (1 << 9),
> - IRQ_NOPROBE = (1 << 10),
> - IRQ_NOREQUEST = (1 << 11),
> - IRQ_NOAUTOEN = (1 << 12),
> - IRQ_NO_BALANCING = (1 << 13),
> - IRQ_MOVE_PCNTXT = (1 << 14),
> - IRQ_NESTED_THREAD = (1 << 15),
> - IRQ_NOTHREAD = (1 << 16),
> - IRQ_PER_CPU_DEVID = (1 << 17),
> - IRQ_IS_POLLED = (1 << 18),
> - IRQ_DISABLE_UNLAZY = (1 << 19),
> + IRQ_TYPE_PROBE = BIT(4),
> +
> + IRQ_LEVEL = BIT(8),
> + IRQ_PER_CPU = BIT(9),
> + IRQ_NOPROBE = BIT(10),
> + IRQ_NOREQUEST = BIT(11),
> + IRQ_NOAUTOEN = BIT(12),
> + IRQ_NO_BALANCING = BIT(13),
> + IRQ_MOVE_PCNTXT = BIT(14),
> + IRQ_NESTED_THREAD = BIT(15),
> + IRQ_NOTHREAD = BIT(16),
> + IRQ_PER_CPU_DEVID = BIT(17),
> + IRQ_IS_POLLED = BIT(18),
> + IRQ_DISABLE_UNLAZY = BIT(19),
> };
>
> #define IRQF_MODIFY_MASK \
> @@ -211,26 +211,26 @@ struct irq_data {
> * IRQD_CAN_RESERVE - Can use reservation mode
> */
> enum {
> - IRQD_TRIGGER_MASK = 0xf,
> - IRQD_SETAFFINITY_PENDING = (1 << 8),
> - IRQD_ACTIVATED = (1 << 9),
> - IRQD_NO_BALANCING = (1 << 10),
> - IRQD_PER_CPU = (1 << 11),
> - IRQD_AFFINITY_SET = (1 << 12),
> - IRQD_LEVEL = (1 << 13),
> - IRQD_WAKEUP_STATE = (1 << 14),
> - IRQD_MOVE_PCNTXT = (1 << 15),
> - IRQD_IRQ_DISABLED = (1 << 16),
> - IRQD_IRQ_MASKED = (1 << 17),
> - IRQD_IRQ_INPROGRESS = (1 << 18),
> - IRQD_WAKEUP_ARMED = (1 << 19),
> - IRQD_FORWARDED_TO_VCPU = (1 << 20),
> - IRQD_AFFINITY_MANAGED = (1 << 21),
> - IRQD_IRQ_STARTED = (1 << 22),
> - IRQD_MANAGED_SHUTDOWN = (1 << 23),
> - IRQD_SINGLE_TARGET = (1 << 24),
> - IRQD_DEFAULT_TRIGGER_SET = (1 << 25),
> - IRQD_CAN_RESERVE = (1 << 26),
> + IRQD_TRIGGER_MASK = GENMASK(3,0),
> + IRQD_SETAFFINITY_PENDING = BIT(8),
> + IRQD_ACTIVATED = BIT(9),
> + IRQD_NO_BALANCING = BIT(10),
> + IRQD_PER_CPU = BIT(11),
> + IRQD_AFFINITY_SET = BIT(12),
> + IRQD_LEVEL = BIT(13),
> + IRQD_WAKEUP_STATE = BIT(14),
> + IRQD_MOVE_PCNTXT = BIT(15),
> + IRQD_IRQ_DISABLED = BIT(16),
> + IRQD_IRQ_MASKED = BIT(17),
> + IRQD_IRQ_INPROGRESS = BIT(18),
> + IRQD_WAKEUP_ARMED = BIT(19),
> + IRQD_FORWARDED_TO_VCPU = BIT(20),
> + IRQD_AFFINITY_MANAGED = BIT(21),
> + IRQD_IRQ_STARTED = BIT(22),
> + IRQD_MANAGED_SHUTDOWN = BIT(23),
> + IRQD_SINGLE_TARGET = BIT(24),
> + IRQD_DEFAULT_TRIGGER_SET = BIT(25),
> + IRQD_CAN_RESERVE = BIT(26),
> };
>
> #define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors)
> @@ -507,14 +507,14 @@ struct irq_chip {
> * IRQCHIP_SUPPORTS_LEVEL_MSI Chip can provide two doorbells for Level MSIs
> */
> enum {
> - IRQCHIP_SET_TYPE_MASKED = (1 << 0),
> - IRQCHIP_EOI_IF_HANDLED = (1 << 1),
> - IRQCHIP_MASK_ON_SUSPEND = (1 << 2),
> - IRQCHIP_ONOFFLINE_ENABLED = (1 << 3),
> - IRQCHIP_SKIP_SET_WAKE = (1 << 4),
> - IRQCHIP_ONESHOT_SAFE = (1 << 5),
> - IRQCHIP_EOI_THREADED = (1 << 6),
> - IRQCHIP_SUPPORTS_LEVEL_MSI = (1 << 7),
> + IRQCHIP_SET_TYPE_MASKED = BIT(0),
> + IRQCHIP_EOI_IF_HANDLED = BIT(1),
> + IRQCHIP_MASK_ON_SUSPEND = BIT(2),
> + IRQCHIP_ONOFFLINE_ENABLED = BIT(3),
> + IRQCHIP_SKIP_SET_WAKE = BIT(4),
> + IRQCHIP_ONESHOT_SAFE = BIT(5),
> + IRQCHIP_EOI_THREADED = BIT(6),
> + IRQCHIP_SUPPORTS_LEVEL_MSI = BIT(7),
> };
>
> #include <linux/irqdesc.h>
> @@ -1007,11 +1007,11 @@ struct irq_chip_generic {
> * @IRQ_GC_BE_IO: Use big-endian register accesses (default: LE)
> */
> enum irq_gc_flags {
> - IRQ_GC_INIT_MASK_CACHE = 1 << 0,
> - IRQ_GC_INIT_NESTED_LOCK = 1 << 1,
> - IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2,
> - IRQ_GC_NO_MASK = 1 << 3,
> - IRQ_GC_BE_IO = 1 << 4,
> + IRQ_GC_INIT_MASK_CACHE = BIT(0),
> + IRQ_GC_INIT_NESTED_LOCK = BIT(1),
> + IRQ_GC_MASK_CACHE_PER_TYPE = BIT(2),
> + IRQ_GC_NO_MASK = BIT(3),
> + IRQ_GC_BE_IO = BIT(4),
> };
>
> /*
>
thanks.
--
~Randy
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