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Message-ID: <20190117063804.GJ25498@builder>
Date: Wed, 16 Jan 2019 22:38:04 -0800
From: Bjorn Andersson <bjorn.andersson@...aro.org>
To: Stephen Boyd <sboyd@...nel.org>
Cc: andy.gross@...aro.org, david.brown@...aro.org,
jassisinghbrar@...il.com, jorge.ramirez-ortiz@...aro.org,
mark.rutland@....com, mturquette@...libre.com, robh+dt@...nel.org,
will.deacon@....com, vkoul@...nel.org, niklas.cassel@...aro.org,
sibis@...eaurora.org, georgi.djakov@...aro.org, arnd@...db.de,
horms+renesas@...ge.net.au, heiko@...ech.de,
enric.balletbo@...labora.com, jagan@...rulasolutions.com,
olof@...om.net, amit.kucheria@...aro.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-clk@...r.kernel.org
Subject: Re: [PATCH 10/13] arm64: dts: qcom: qcs404: Add HFPLL node
On Mon 17 Dec 11:39 PST 2018, Stephen Boyd wrote:
> Quoting Jorge Ramirez-Ortiz (2018-12-17 01:46:27)
> > The high frequency pll functionality is required to enable CPU
> > frequency scaling operation.
> >
> > Co-developed-by: Niklas Cassel <niklas.cassel@...aro.org>
> > Signed-off-by: Niklas Cassel <niklas.cassel@...aro.org>
> > Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@...aro.org>
> > ---
> > arch/arm64/boot/dts/qcom/qcs404.dtsi | 9 +++++++++
> > 1 file changed, 9 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> > index 4594fea7..ec3f6c7 100644
> > --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
> > @@ -375,6 +375,15 @@
> > #mbox-cells = <1>;
> > };
> >
> > + apcs_hfpll: clock-controller@...16000 {
>
> Drop leading 0 on unit address please.
>
> > + compatible = "qcom,hfpll";
> > + reg = <0x0b016000 0x30>;
>
> Wow that is small!
>
I double checked and it's actually 0x34, but the last register is
protected.
Regards,
Bjorn
> > + #clock-cells = <0>;
> > + clock-output-names = "apcs_hfpll";
> > + clocks = <&xo_board>;
> > + clock-names = "xo";
> > + };
> > +
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