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Message-Id: <20190118010634.27399-6-paul@crapouillou.net>
Date: Thu, 17 Jan 2019 22:06:32 -0300
From: Paul Cercueil <paul@...pouillou.net>
To: David Woodhouse <dwmw2@...radead.org>,
Brian Norris <computersforpeace@...il.com>,
Boris Brezillon <bbrezillon@...nel.org>,
Marek Vasut <marek.vasut@...il.com>,
Richard Weinberger <richard@....at>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Ralf Baechle <ralf@...ux-mips.org>,
Paul Burton <paul.burton@...s.com>,
James Hogan <jhogan@...nel.org>,
Miquel Raynal <miquel.raynal@...tlin.com>,
Harvey Hunt <harveyhuntnexus@...il.com>
Cc: linux-mtd@...ts.infradead.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-mips@...r.kernel.org,
Paul Cercueil <paul@...pouillou.net>
Subject: [PATCH 6/8] mtd: rawnand: jz4780-bch: Don't set clock rate in driver
This should be done in devicetree. Besides, it prevents us from
supporting other SoCs which don't use the same clock frequency for the
BCH hardware.
Signed-off-by: Paul Cercueil <paul@...pouillou.net>
---
drivers/mtd/nand/raw/jz4780_bch.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/drivers/mtd/nand/raw/jz4780_bch.c b/drivers/mtd/nand/raw/jz4780_bch.c
index 7e4e5e627603..161d3821e1c4 100644
--- a/drivers/mtd/nand/raw/jz4780_bch.c
+++ b/drivers/mtd/nand/raw/jz4780_bch.c
@@ -57,8 +57,6 @@
#define BCH_BHINT_UNCOR BIT(1)
#define BCH_BHINT_ERR BIT(0)
-#define BCH_CLK_RATE (200 * 1000 * 1000)
-
/* Timeout for BCH calculation/correction. */
#define BCH_TIMEOUT_US 100000
@@ -348,8 +346,6 @@ static int jz4780_bch_probe(struct platform_device *pdev)
return PTR_ERR(bch->clk);
}
- clk_set_rate(bch->clk, BCH_CLK_RATE);
-
mutex_init(&bch->lock);
bch->dev = dev;
--
2.11.0
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