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Message-Id: <1548106951-4811-5-git-send-email-kan.liang@linux.intel.com>
Date: Mon, 21 Jan 2019 13:42:31 -0800
From: kan.liang@...ux.intel.com
To: x86@...nel.org, linux-kernel@...r.kernel.org, tglx@...utronix.de,
bp@...en8.de, peterz@...radead.org, mingo@...hat.com
Cc: ak@...ux.intel.com, eranian@...gle.com,
Kan Liang <kan.liang@...ux.intel.com>
Subject: [PATCH V6 5/5] perf/x86/intel: Add counter freezing quirk for Goldmont
From: Kan Liang <kan.liang@...ux.intel.com>
A microcode patch is also needed for Goldmont while counter freezing
feature is enabled. Otherwise, there will be some issues, e.g. PMI lost.
Signed-off-by: Kan Liang <kan.liang@...ux.intel.com>
---
Changes since V5:
- Apply the new name
arch/x86/events/intel/core.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index bad19a9..3eacdf6 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -3918,8 +3918,12 @@ static __init void intel_nehalem_quirk(void)
}
static const struct x86_cpu_desc counter_freezing_ucodes[] = {
- INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_PLUS, 1, 0x00000028),
- INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_PLUS, 8, 0x00000006),
+ INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT, 2, 0x0000000e),
+ INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT, 9, 0x0000002e),
+ INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT, 10, 0x00000008),
+ INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_X, 1, 0x00000028),
+ INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_PLUS, 1, 0x00000028),
+ INTEL_CPU_DESC(INTEL_FAM6_ATOM_GOLDMONT_PLUS, 8, 0x00000006),
{}
};
@@ -4293,6 +4297,7 @@ __init int intel_pmu_init(void)
case INTEL_FAM6_ATOM_GOLDMONT:
case INTEL_FAM6_ATOM_GOLDMONT_X:
+ x86_add_quirk(intel_counter_freezing_quirk);
memcpy(hw_cache_event_ids, glm_hw_cache_event_ids,
sizeof(hw_cache_event_ids));
memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs,
--
2.7.4
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