linux-kernel - Re: [PATCH 3/4] dma-buf: add support for mapping with dma mapping attributes

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Tue, 22 Jan 2019 10:06:07 -0600
From:   "Andrew F. Davis" <afd@...com>
To:     Liam Mark <lmark@...eaurora.org>,
        Christoph Hellwig <hch@...radead.org>
CC:     Laura Abbott <labbott@...hat.com>, <sumit.semwal@...aro.org>,
        <arve@...roid.com>, <tkjos@...roid.com>, <maco@...roid.com>,
        <joel@...lfernandes.org>, <christian@...uner.io>,
        <devel@...verdev.osuosl.org>, <dri-devel@...ts.freedesktop.org>,
        <linaro-mm-sig@...ts.linaro.org>, <linux-kernel@...r.kernel.org>,
        <john.stultz@...aro.org>
Subject: Re: [PATCH 3/4] dma-buf: add support for mapping with dma mapping
 attributes

On 1/21/19 4:12 PM, Liam Mark wrote:
> On Mon, 21 Jan 2019, Christoph Hellwig wrote:
> 
>> On Mon, Jan 21, 2019 at 11:44:10AM -0800, Liam Mark wrote:
>>> The main use case is for allowing clients to pass in 
>>> DMA_ATTR_SKIP_CPU_SYNC in order to skip the default cache maintenance 
>>> which happens in dma_buf_map_attachment and dma_buf_unmap_attachment. In 
>>> ION the buffers aren't usually accessed from the CPU so this allows 
>>> clients to often avoid doing unnecessary cache maintenance.
>>
>> This can't work.  The cpu can still easily speculate into this area.
> 
> Can you provide more detail on your concern here.
> The use case I am thinking about here is a cached buffer which is accessed 
> by a non IO-coherent device (quite a common use case for ION).
> 
> Guessing on your concern:
> The speculative access can be an issue if you are going to access the 
> buffer from the CPU after the device has written to it, however if you 
> know you aren't going to do any CPU access before the buffer is again 
> returned to the device then I don't think the speculative access is a 
> concern.
> 
>> Moreover in general these operations should be cheap if the addresses
>> aren't cached.
>>
> 
> I am thinking of use cases with cached buffers here, so CMO isn't cheap.
> 

These buffers are cacheable, not cached, if you haven't written anything
the data wont actually be in cache. And in the case of speculative cache
filling the lines are marked clean. In either case the only cost is the
little 7 instruction loop calling the clean/invalidate instruction (dc
civac for ARMv8) for the cache-lines. Unless that is the cost you are
trying to avoid?

In that case if you are mapping and unmapping so much that the little
CMO here is hurting performance then I would argue your usage is broken
and needs to be re-worked a bit.

Andrew

> 
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> a Linux Foundation Collaborative Project
>