linux-kernel - Re: [PATCH v1 3/8] arm64: dts: sdm845: Add UFS PHY reset

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Mon, 21 Jan 2019 18:25:49 -0600
From:   Rob Herring <robh@...nel.org>
To:     Evan Green <evgreen@...omium.org>
Cc:     Andy Gross <andy.gross@...aro.org>,
        Kishon Vijay Abraham I <kishon@...com>,
        Can Guo <cang@...eaurora.org>,
        Douglas Anderson <dianders@...omium.org>,
        Asutosh Das <asutoshd@...eaurora.org>,
        Stephen Boyd <swboyd@...omium.org>,
        Vivek Gautam <vivek.gautam@...eaurora.org>,
        devicetree@...r.kernel.org, linux-arm-msm@...r.kernel.org,
        linux-kernel@...r.kernel.org, David Brown <david.brown@...aro.org>,
        Mark Rutland <mark.rutland@....com>
Subject: Re: [PATCH v1 3/8] arm64: dts: sdm845: Add UFS PHY reset

On Fri, Jan 11, 2019 at 03:01:24PM -0800, Evan Green wrote:
> Wire up the reset controller in the Qcom UFS controller for the PHY.
> This will be used to toggle PHY reset during initialization of the PHY.
> 
> Signed-off-by: Evan Green <evgreen@...omium.org>
> ---
> This commit is based atop the series at [1]. Patches 1 and 2 of that
> series have landed, but 3, 4, and 5 are still outstanding.
> 
> [1] https://lore.kernel.org/lkml/20181210192826.241350-1-evgreen@chromium.org/
> 
>  arch/arm64/boot/dts/qcom/sdm845.dtsi | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index b29332b265d9e..029ab66405cf4 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -990,6 +990,7 @@
>  			phy-names = "ufsphy";
>  			lanes-per-direction = <2>;
>  			power-domains = <&gcc UFS_PHY_GDSC>;
> +			#reset-cells = <1>;

Is this documented?

>  
>  			clock-names =
>  				"core_clk",
> @@ -1033,6 +1034,8 @@
>  			clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
>  				 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
>  
> +			resets = <&ufs_mem_hc 0>;
> +			reset-names = "ufsphy";
>  			status = "disabled";
>  
>  			ufs_mem_phy_lanes: lanes@...7400 {
> -- 
> 2.18.1
>