linux-kernel - Re: [PATCH 1/6] dt-bindings: timer: add Tegra210 timer

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Message-ID: <709e24fa-02e1-96ea-2b20-acf150caff00@nvidia.com>
Date:   Fri, 25 Jan 2019 12:06:47 +0000
From:   Jon Hunter <jonathanh@...dia.com>
To:     Joseph Lo <josephl@...dia.com>,
        Thierry Reding <thierry.reding@...il.com>
CC:     <devicetree@...r.kernel.org>,
        Daniel Lezcano <daniel.lezcano@...aro.org>,
        <linux-kernel@...r.kernel.org>, <linux-tegra@...r.kernel.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH 1/6] dt-bindings: timer: add Tegra210 timer


On 25/01/2019 12:01, Jon Hunter wrote:
> 
> On 25/01/2019 03:23, Joseph Lo wrote:
>> Hi Jon,
>>
>> Thanks for reviewing.
>>
>> On 1/24/19 6:30 PM, Jon Hunter wrote:
>>>
>>> On 07/01/2019 03:28, Joseph Lo wrote:
>>>> The Tegra210 timer provides fourteen 29-bit timer counters and one
>>>> 32-bit
>>>> timestamp counter. The TMRs run at either a fixed 1 MHz clock rate
>>>> derived
>>>> from the oscillator clock (TMR0-TMR9) or directly at the oscillator
>>>> clock
>>>> (TMR10-TMR13). Each TMR can be programmed to generate one-shot periodic,
>>>> or watchdog interrupts.
>>>>
>>>> Cc: Daniel Lezcano <daniel.lezcano@...aro.org>
>>>> Cc: Thomas Gleixner <tglx@...utronix.de>
>>>> Cc: linux-kernel@...r.kernel.org
>>>> Cc: devicetree@...r.kernel.org
>>>> Signed-off-by: Joseph Lo <josephl@...dia.com>
>>>> ---
>>>>   .../bindings/timer/nvidia,tegra210-timer.txt  | 25 +++++++++++++++++++
>>>>   1 file changed, 25 insertions(+)
>>>>   create mode 100644
>>>> Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt
>>>>
>>>> diff --git
>>>> a/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt
>>>> b/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt
>>>> new file mode 100644
>>>> index 000000000000..ba511220a669
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/timer/nvidia,tegra210-timer.txt
>>>> @@ -0,0 +1,25 @@
>>>> +NVIDIA Tegra210 timer
>>>> +
>>>> +The Tegra210 timer provides fourteen 29-bit timer counters and one
>>>> 32-bit
>>>> +timestamp counter. The TMRs run at either a fixed 1 MHz clock rate
>>>> derived
>>>> +from the oscillator clock (TMR0-TMR9) or directly at the oscillator
>>>> clock
>>>> +(TMR10-TMR13). Each TMR can be programmed to generate one-shot,
>>>> periodic,
>>>> +or watchdog interrupts.
>>>> +
>>>> +Required properties:
>>>> +- compatible : "nvidia,tegra210-timer".
>>>> +- reg : Specifies base physical address and size of the registers.
>>>> +- interrupts : A list of 4 interrupts; one per each of TMR10 through
>>>> TMR13.
>>>
>>> Why do we only add the interrupts for TMR10 - TMR13? What about the
>>> others?
>>>
>>
>> The others (TMR0-TMR9) are occupied for other usages. TMR5 is occupied
>> for the watchdog timer in the upstream kernel. And others (still in
>> TMR0-TMR9) are occupied for different usages in our downstream kernel.
> 
> Where is TMR5 reserved for the watchdog? I don't see this?

I see it now, it is hard-coded in the driver. I was looking at arm64 to
see where it is used.

Cheers
Jon

-- 
nvpublic