linux-kernel - [PATCH 00/10] Optimise TLB miss handlers on 603/e300

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Date:   Fri, 25 Jan 2019 12:34:00 +0000 (UTC)
From:   Christophe Leroy <christophe.leroy@....fr>
To:     Benjamin Herrenschmidt <benh@...nel.crashing.org>,
        Paul Mackerras <paulus@...ba.org>,
        Michael Ellerman <mpe@...erman.id.au>,
        joakim.tjernlund@...inera.com
Cc:     linux-kernel@...r.kernel.org, linuxppc-dev@...ts.ozlabs.org
Subject: [PATCH 00/10] Optimise TLB miss handlers on 603/e300

The purpose of this serie is to optimise the handling of
TLB misses on the 603/e300.

Today the TLB miss handlers are implemented by more or less
copying the actions performed by the hash page handlers used
on processors having HASH pagetable.

This serie brings some simplification.

Christophe Leroy (10):
  powerpc: simplify BDI switch
  powerpc/603: Store PGDIR physical address in a SPRG
  powerpc/603: use physical address directly in TLB miss handlers.
  powerpc/hash32: use physical address directly in hash handlers.
  powerpc/603: Don't handle kernel page TLB misses when not need
  powerpc/603: Don't handle _PAGE_RW and _PAGE_DIRTY on ITLB misses
  powerpc/603: let's handle PAGE_DIRTY directly
  powerpc/603: Don't worry about _PAGE_USER in TLB miss handlers
  powerpc/603: don't handle PAGE_ACCESSED in TLB miss handlers.
  powerpc/book3s32: Reorder _PAGE_XXX flags to simplify TLB handling

 arch/powerpc/include/asm/book3s/32/hash.h |  8 +--
 arch/powerpc/include/asm/mmu.h            |  2 +
 arch/powerpc/include/asm/reg.h            |  1 +
 arch/powerpc/kernel/cpu_setup_6xx.S       |  4 ++
 arch/powerpc/kernel/head_32.S             | 97 ++++++++++++++-----------------
 arch/powerpc/kernel/head_40x.S            |  5 +-
 arch/powerpc/kernel/head_8xx.S            |  1 +
 arch/powerpc/mm/8xx_mmu.c                 |  7 +--
 arch/powerpc/mm/hash_low_32.S             | 68 +++++++++-------------
 arch/powerpc/mm/ppc_mmu_32.c              |  6 +-
 10 files changed, 93 insertions(+), 106 deletions(-)

-- 
2.13.3