linux-kernel - [PATCH] clk: ingenic: jz4740: Fix gating of UDC clock

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Message-Id: <20190125153436.13517-1-paul@crapouillou.net>
Date:   Fri, 25 Jan 2019 12:34:36 -0300
From:   Paul Cercueil <paul@...pouillou.net>
To:     Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>
Cc:     linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
        Paul Cercueil <paul@...pouillou.net>
Subject: [PATCH] clk: ingenic: jz4740: Fix gating of UDC clock

The UDC clock is gated when the bit is cleared, not when it is set.

Signed-off-by: Paul Cercueil <paul@...pouillou.net>
Tested-by: Artur Rojek <contact@...ur-rojek.eu>
---
 drivers/clk/ingenic/jz4740-cgu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/ingenic/jz4740-cgu.c b/drivers/clk/ingenic/jz4740-cgu.c
index d8ac7f2e183a..5d0d5be1e6a7 100644
--- a/drivers/clk/ingenic/jz4740-cgu.c
+++ b/drivers/clk/ingenic/jz4740-cgu.c
@@ -165,7 +165,7 @@ static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
 		.parents = { JZ4740_CLK_EXT, JZ4740_CLK_PLL_HALF, -1, -1 },
 		.mux = { CGU_REG_CPCCR, 29, 1 },
 		.div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 },
-		.gate = { CGU_REG_SCR, 6 },
+		.gate = { CGU_REG_SCR, 6, true },
 	},
 
 	/* Gate-only clocks */
-- 
2.20.1