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Message-ID: <0aa09e77-1454-9eaf-ef67-b00518e6f2d2@oracle.com>
Date:   Mon, 28 Jan 2019 16:28:25 +0800
From:   Zhenzhong Duan <zhenzhong.duan@...cle.com>
To:     Thomas Gleixner <tglx@...utronix.de>
Cc:     linux-kernel@...r.kernel.org, mingo@...hat.com,
        konrad.wilk@...cle.com, x86@...nel.org, srinivas.eeda@...cle.com,
        bp@...e.de, tim.c.chen@...ux.intel.com, peterz@...radead.org,
        hpa@...or.com
Subject: Re: [PATCH] x86/speculation: Update TIF_SPEC_IB before ibpb barrier

On 2019/1/26 2:03, Thomas Gleixner wrote:
> On Fri, 25 Jan 2019, Thomas Gleixner wrote:
>> On Wed, 23 Jan 2019, Thomas Gleixner wrote:
>>
>>> On Fri, 18 Jan 2019, Zhenzhong Duan wrote:
>>>
>>>> When a task is set for updating TIF_SPEC_IB throuth SECCOMP by others
>>>> and it's scheduled in the first time, a stale TIF_SPEC_IB value is
>>>> picked in cond_ibpb(). This is due to TIF_SPEC_IB is updated later at
>>>> __switch_to_xtra().
>>>>
>>>> Add an extra call to speculation_ctrl_update_tif() to update it before
>>>> IBPB barrier.
>>>
>>> Errm. No. It adds that call to speculation_ctrl_update_tif() for every
>>> mm switch, most of the time for nothing.
>>>
>>> If at all, and we discussed that before and decided not to worry about it
>>> (because it gets fixed up on the next context switch), then you want to
>>> handle ibpb() from there:
>>
>> Actually we need to do that. It's not only the scheduled in first
>> problem. That whole thing might become completely stale in either
>> direction. Care to whip up a patch?
> 
> Bah, nonsense. Brain was clearly still out for lunch and I confused IBPB
> and STIBP for a moment. cond_ibpb() is the thing issues in switch_mm() and
> that is not leaving a stale MSR around because we only write to it when we
> need the barrier. The bit is not stale because the barrier is only issued
> with the write. The bit has not to be cleared.
> 
> So the only 'issue' what happens is that switch_to() either issues a
> barrier too much or misses one. That's really not a problem.

Ok, yes, the purpose of this patch is to avoid the one missed barrier.
Thanks for your reply.

Zhenzhong

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