linux-kernel - Re: [PATCH] KVM: x86: Sync the pending Posted-Interrupts

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <ac760e76-f586-411e-134d-f7d424160831@redhat.com>
Date:   Mon, 28 Jan 2019 10:18:14 +0100
From:   Paolo Bonzini <pbonzini@...hat.com>
To:     "Kang, Luwei" <luwei.kang@...el.com>,
        "kvm@...r.kernel.org" <kvm@...r.kernel.org>
Cc:     "rkrcmar@...hat.com" <rkrcmar@...hat.com>,
        "tglx@...utronix.de" <tglx@...utronix.de>,
        "mingo@...hat.com" <mingo@...hat.com>,
        "bp@...en8.de" <bp@...en8.de>, "hpa@...or.com" <hpa@...or.com>,
        "x86@...nel.org" <x86@...nel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] KVM: x86: Sync the pending Posted-Interrupts

On 28/01/19 09:08, Kang, Luwei wrote:
>> However, you should at least change the comment in vcpu_enter_guest to mention "before reading PIR" instead of "before reading
>> PIR.ON".
> 
> Will do that. I think the "checking PIR.ON" should be PID.ON. I will fix it.

Yes.

>> Alternatively, would it be possible to instead set ON when SN is
>> cleared?  The clearing of SN is in pi_clear_sn, and you would have instead
>> something like

> 
> SN is cleared when the corresponding vCPU is running on pCPU. I think we can't set ON when SN is cleared.  Because there have some words in VT-d spec 9.12:
> If ON is set at the time of hardware posting an interrupt to PIR field, notification event is not generated.

This is okay, because you are setting ON and vmx_sync_pir_to_irr will
read ON before the next vCPU entry and move the interrupts from PIR to IRR.

Paolo

>>
>> 	WRITE_ONCE(u16 *)&pi_desc->on_sn, POSTED_INTR_ON);
> 
> We already have a function  (pi_test_on) to check the bit of POSTED_INTR_ON. So I think it is unnecessary.
> 
> Thanks,
> Luwei Kang
> 
>>
>> where on_sn is added to struct pi_desc like this:
>>
>> @@ -61,4 +60,5 @@ struct pi_desc {
>>  			u32	ndst;
>>  		};
>> +		u16 on_sn;
>>  		u64 control;
>>  	};
>>
>> Paolo