linux-kernel - Re: [PATCH V3,0/8] make mt7623 clock of HDMI stable

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Message-ID: <1548667676.10401.17.camel@mtksdaap41>
Date:   Mon, 28 Jan 2019 17:27:56 +0800
From:   CK Hu <ck.hu@...iatek.com>
To:     Wangyan Wang <wangyan.wang@...iatek.com>
CC:     Michael Turquette <mturquette@...libre.com>,
        Matthias Brugger <matthias.bgg@...il.com>,
        Stephen Boyd <sboyd@...nel.org>,
        Philipp Zabel <p.zabel@...gutronix.de>,
        David Airlie <airlied@...ux.ie>,
        Sean Wang <sean.wang@...iatek.com>,
        Ryder Lee <ryder.lee@...iatek.com>,
        "Colin Ian King" <colin.king@...onical.com>,
        <linux-clk@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-mediatek@...ts.infradead.org>,
        <dri-devel@...ts.freedesktop.org>, <jitao.shi@...iatek.com>,
        <bibby.hsieh@...iatek.com>, <srv_heupstream@...iatek.com>
Subject: Re: [PATCH V3,0/8] make mt7623 clock of HDMI stable

Hi, Wangyan:

How do you prove that this series would make mt7623 HDMI clock more
stable? By experience result? I would like to prove it by the source
code.

Does 'stable' means that hardware could generate the frequency most
close to the target frequency? If it does, I think you could compare the
frequency generated by original code and applying this series for all
the usually-used frequency. I also need you to show the clock tree and
all setting of each divider so we could review that is this series good
enough. Also, describe these in cover latter.

You have mail to dri-devel [1] and linux-mediatek [2], but these patches
does not show in web site. Maybe your mail is not plain text, please fix
this and resend patches.

[1] https://lists.freedesktop.org/archives/dri-devel/
[2] http://lists.infradead.org/pipermail/linux-mediatek/

Regards,
CK

On Fri, 2019-01-25 at 12:01 +0800, Wangyan Wang wrote:
> V3 adopt maintainer's suggestion.
> Here is the change list between V2 & V3:
> 1. add "Signed-off-by: wangyan wang <wangyan.wang@...iatek.com>"
> in commit message
> 
> 2. add modify description in patch 
> "drm/mediatek: fix the rate and divder ..."
>  
> chunhui dai (8):
>   drm/mediatek: recalculate hdmi phy clock of MT2701 by querying
>     hardware
>   drm/mediatek: move the setting of fixed divider
>   drm/mediatek: using different flags of clk for HDMI phy
>   drm/mediatek: fix the rate and divder of hdmi phy for MT2701
>   clk: mediatek: add MUX_GATE_FLAGS_2
>   clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel
>   drm/mediatek: using new factor for tvdpll in MT2701
>   drm/mediatek: fix the rate of parent for hdmi phy in MT2701
> 
>  drivers/clk/mediatek/clk-mt2701.c             |  4 +-
>  drivers/clk/mediatek/clk-mtk.c                |  2 +-
>  drivers/clk/mediatek/clk-mtk.h                | 20 +++++--
>  drivers/gpu/drm/mediatek/mtk_dpi.c            |  8 +--
>  drivers/gpu/drm/mediatek/mtk_hdmi_phy.c       | 34 +++--------
>  drivers/gpu/drm/mediatek/mtk_hdmi_phy.h       |  7 +--
>  .../gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c    | 56 +++++++++++++++++--
>  .../gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c    | 23 ++++++++
>  8 files changed, 102 insertions(+), 52 deletions(-)
>