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Message-ID: <CY4PR02MB2709C078D872F2C1ABF82DF2A7960@CY4PR02MB2709.namprd02.prod.outlook.com>
Date: Mon, 28 Jan 2019 11:16:55 +0000
From: Vishal Sagar <vsagar@...inx.com>
To: Hyun Kwon <hyunk@...inx.com>,
Vishal Sagar <vishal.sagar@...inx.com>
CC: Hyun Kwon <hyunk@...inx.com>,
"laurent.pinchart@...asonboard.com"
<laurent.pinchart@...asonboard.com>,
"mchehab@...nel.org" <mchehab@...nel.org>,
"robh+dt@...nel.org" <robh+dt@...nel.org>,
"mark.rutland@....com" <mark.rutland@....com>,
Michal Simek <michals@...inx.com>,
"linux-media@...r.kernel.org" <linux-media@...r.kernel.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"sakari.ailus@...ux.intel.com" <sakari.ailus@...ux.intel.com>,
"hans.verkuil@...co.com" <hans.verkuil@...co.com>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
Dinesh Kumar <dineshk@...inx.com>,
Sandip Kothari <sandipk@...inx.com>
Subject: RE: [PATCH v2 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI
CSI-2 Rx Subsystem
Hi Hyun,
Thanks for the review.
> -----Original Message-----
> From: Hyun Kwon [mailto:hyun.kwon@...inx.com]
> Sent: Saturday, January 26, 2019 7:45 AM
> To: Vishal Sagar <vishal.sagar@...inx.com>
> Cc: Hyun Kwon <hyunk@...inx.com>; laurent.pinchart@...asonboard.com;
> mchehab@...nel.org; robh+dt@...nel.org; mark.rutland@....com; Michal
> Simek <michals@...inx.com>; linux-media@...r.kernel.org;
> devicetree@...r.kernel.org; sakari.ailus@...ux.intel.com;
> hans.verkuil@...co.com; linux-arm-kernel@...ts.infradead.org; linux-
> kernel@...r.kernel.org; Dinesh Kumar <dineshk@...inx.com>; Sandip Kothari
> <sandipk@...inx.com>
> Subject: Re: [PATCH v2 1/2] media: dt-bindings: media: xilinx: Add Xilinx MIPI
> CSI-2 Rx Subsystem
>
> Hi Vishal,
>
> Thanks for the patch.
>
> On Fri, 2019-01-25 at 09:52:56 -0800, Vishal Sagar wrote:
> > Add bindings documentation for Xilinx MIPI CSI-2 Rx Subsystem.
> >
> > The Xilinx MIPI CSI-2 Rx Subsystem consists of a CSI-2 Rx controller, a
> > DPHY in Rx mode, an optional I2C controller and a Video Format Bridge.
> >
> > Signed-off-by: Vishal Sagar <vishal.sagar@...inx.com>
> > ---
> > v2
> > - updated the compatible string to latest version supported
> > - removed DPHY related parameters
> > - added CSI v2.0 related property (including VCX for supporting upto 16
> > virtual channels).
> > - modified csi-pxl-format from string to unsigned int type where the value
> > is as per the CSI specification
> > - Defined port 0 and port 1 as sink and source ports.
> > - Removed max-lanes property as suggested by Rob and Sakari
> >
> > .../bindings/media/xilinx/xlnx,csi2rxss.txt | 105
> +++++++++++++++++++++
> > 1 file changed, 105 insertions(+)
> > create mode 100644
> Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
> >
> > diff --git a/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
> b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
> > new file mode 100644
> > index 0000000..98781cf
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/xilinx/xlnx,csi2rxss.txt
> > @@ -0,0 +1,105 @@
> > +Xilinx MIPI CSI2 Receiver Subsystem Device Tree Bindings
> > +--------------------------------------------------------
> > +
> > +The Xilinx MIPI CSI2 Receiver Subsystem is used to capture MIPI CSI2 traffic
> > +from compliant camera sensors and send the output as AXI4 Stream video
> data
> > +for image processing.
> > +
> > +The subsystem consists of a MIPI DPHY in slave mode which captures the
> > +data packets. This is passed along the MIPI CSI2 Rx IP which extracts the
> > +packet data. The Video Format Bridge (VFB) converts this data to AXI4
> Stream
> > +video data.
> > +
> > +For more details, please refer to PG232 Xilinx MIPI CSI-2 Receiver Subsystem.
> > +
> > +Required properties:
> > +--------------------
> > +- compatible: Must contain "xlnx,mipi-csi2-rx-subsystem-4.0".
> > +- reg: Physical base address and length of the registers set for the device.
> > +- interrupt-parent: specifies the phandle to the parent interrupt controller
> > +- interrupts: Property with a value describing the interrupt number.
> > +- clocks: List of phandles to AXI Lite, Video and 200 MHz DPHY clocks.
> > +- clock-names: Must contain "lite_aclk", "video_aclk" and "dphy_clk_200M"
> in
> > + the same order as clocks listed in clocks property.
> > +- xlnx,csi-pxl-format: This denotes the CSI Data type selected in hw design.
> > + Packets other than this data type (except for RAW8 and User defined data
> > + types) will be filtered out. Possible values are as below -
> > + 0x1E - YUV4228B
> > + 0x1F - YUV42210B
> > + 0x20 - RGB444
> > + 0x21 - RGB555
> > + 0x22 - RGB565
> > + 0x23 - RGB666
> > + 0x24 - RGB888
> > + 0x28 - RAW6
> > + 0x29 - RAW7
> > + 0x2A - RAW8
> > + 0x2B - RAW10
> > + 0x2C - RAW12
> > + 0x2D - RAW14
> > + 0x2E - RAW16
> > + 0x2F - RAW20
> > +- xlnx,vfb: This is present when Video Format Bridge is enabled.
>
> Isn't this optional as well?
Ok this will be updated in next revision.
When this property is not present, the driver probe will fail as the output of the IP will not match the media bus formats.
>
> > +
> > +Optional properties:
> > +--------------------
> > +- xlnx,en-csi-v2-0: Present if CSI v2 is enabled in IP configuration.
> > +- xlnx,en-vcx: When present, there are maximum 16 virtual channels, else
> > + only 4. This is present only if xlnx,en-csi-v2-0 is present.
> > +- xlnx,en-active-lanes: Enable Active lanes configuration in Protocol
> > + Configuration Register.
> > +- xlnx,cfa-pattern: This goes in the sink port to indicate bayer pattern.
> > + Valid values are "bggr", "rggb", "gbrg" and "grbg".
> > +
> > +Ports
> > +-----
> > +The device node shall contain two 'port' child nodes as defined in
> > +Documentation/devicetree/bindings/media/video-interfaces.txt.
> > +
> > +The port@0 is sink port and shall connect to CSI2 source like camera.
> > +It must have the data-lanes property. It may have the xlnx,cfa-pattern
> > +property to indicate bayer pattern of source.
>
> These two properties better be spelled out properly. Maybe better to mention
> the data-lanes is from video-interfaces.txt.
Ok. I will document each port with its properties under a Ports section
And send it across in the next revision.
Regards
Vishal Sagar
>
> Thanks,
> -hyun
>
> > +
> > +The port@1 is source port could be connected to any video processing IP
> > +which can work with AXI4 Stream data.
> > +
> > +Both ports must have remote-endpoints.
> > +
> > +Example:
> > +
> > + csiss_1: csiss@...20000 {
> > + compatible = "xlnx,mipi-csi2-rx-subsystem-4.0";
> > + reg = <0x0 0xa0020000 0x0 0x10000>;
> > + interrupt-parent = <&gic>;
> > + interrupts = <0 95 4>;
> > + xlnx,csi-pxl-format = <0x2a>;
> > + xlnx,vfb;
> > + xlnx,en-active-lanes;
> > + xlnx,en-csi-v2-0;
> > + xlnx,en-vcx;
> > + clock-names = "lite_aclk", "dphy_clk_200M", "video_aclk";
> > + clocks = <&misc_clk_0>, <&misc_clk_1>, <&misc_clk_2>;
> > +
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + port@0 {
> > + /* Sink port */
> > + reg = <0>;
> > + xlnx,cfa-pattern = "bggr"
> > + csiss_in: endpoint {
> > + data-lanes = <1 2 3 4>;
> > + /* MIPI CSI2 Camera handle */
> > + remote-endpoint = <&camera_out>;
> > + };
> > + };
> > + port@1 {
> > + /* Source port */
> > + reg = <1>;
> > + csiss_out: endpoint {
> > + remote-endpoint = <&vproc_in>;
> > + };
> > + };
> > + };
> > + };
> > --
> > 2.7.4
> >
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