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Message-Id: <1548789745.2531.0@crapouillou.net>
Date:   Tue, 29 Jan 2019 16:22:25 -0300
From:   Paul Cercueil <paul@...pouillou.net>
To:     Stephen Boyd <sboyd@...nel.org>
Cc:     Michael Turquette <mturquette@...libre.com>,
        linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] clk: ingenic: jz4740: Fix gating of UDC clock

Hi,

Le mar. 29 janv. 2019 à 15:13, Stephen Boyd <sboyd@...nel.org> a 
écrit :
> Quoting Paul Cercueil (2019-01-25 11:24:58)
>>  Hi,
>> 
>> 
>>  On Fri, Jan 25, 2019 at 3:55 PM, Stephen Boyd <sboyd@...nel.org> 
>> wrote:
>>  > Quoting Paul Cercueil (2019-01-25 07:34:36)
>>  >>  The UDC clock is gated when the bit is cleared, not when it is 
>> set.
>>  >>
>>  >>  Signed-off-by: Paul Cercueil <paul@...pouillou.net
>>  >> <mailto:paul@...pouillou.net>>
>>  >>  Tested-by: Artur Rojek <contact@...ur-rojek.eu
>>  >> <mailto:contact@...ur-rojek.eu>>
>>  >>  ---
>>  >
>>  > Any Fixes tag for this?
>>  >
>> 
>>  Fixes: 2b555a4b9cae
>> 
>>  Should I resend?
>> 
> 
> No need to resend. Is this fixing something that's broken in the 
> v5.0-rc
> series? I'm trying to understand if this is a critical fix or a
> non-critical fix that can bake until the next release cycle.

It's been broken for one year and nobody noticed, it can wait for 5.1.

-Paul

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