linux-kernel - [PATCH 4.20 075/117] EDAC, altera: Fix S10 persistent register offset

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Message-Id: <20190129113211.253650252@linuxfoundation.org>
Date:   Tue, 29 Jan 2019 12:35:26 +0100
From:   Greg Kroah-Hartman <gregkh@...uxfoundation.org>
To:     linux-kernel@...r.kernel.org
Cc:     Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        stable@...r.kernel.org, Thor Thayer <thor.thayer@...ux.intel.com>,
        Borislav Petkov <bp@...e.de>,
        James Morse <james.morse@....com>,
        Mauro Carvalho Chehab <mchehab@...nel.org>,
        devicetree@...r.kernel.org, dinguyen@...nel.org,
        linux-edac <linux-edac@...r.kernel.org>, mark.rutland@....com,
        robh+dt@...nel.org
Subject: [PATCH 4.20 075/117] EDAC, altera: Fix S10 persistent register offset

4.20-stable review patch.  If anyone has any objections, please let me know.

------------------

From: Thor Thayer <thor.thayer@...ux.intel.com>

commit 245b6c6558128327d330549b23d09594c46f58df upstream.

Correct the persistent register offset where address and status are
stored.

Fixes: 08f08bfb7b4c ("EDAC, altera: Merge Stratix10 into the Arria10 SDRAM probe routine")
Signed-off-by: Thor Thayer <thor.thayer@...ux.intel.com>
Signed-off-by: Borislav Petkov <bp@...e.de>
Cc: James Morse <james.morse@....com>
Cc: Mauro Carvalho Chehab <mchehab@...nel.org>
Cc: devicetree@...r.kernel.org
Cc: dinguyen@...nel.org
Cc: linux-edac <linux-edac@...r.kernel.org>
Cc: mark.rutland@....com
Cc: robh+dt@...nel.org
Cc: stable <stable@...r.kernel.org>
Link: https://lkml.kernel.org/r/1548179287-21760-2-git-send-email-thor.thayer@linux.intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@...uxfoundation.org>

---
 drivers/edac/altera_edac.h |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

--- a/drivers/edac/altera_edac.h
+++ b/drivers/edac/altera_edac.h
@@ -295,8 +295,8 @@ struct altr_sdram_mc_data {
 #define S10_SYSMGR_ECC_INTSTAT_DERR_OFST  0xA0
 
 /* Sticky registers for Uncorrected Errors */
-#define S10_SYSMGR_UE_VAL_OFST            0x120
-#define S10_SYSMGR_UE_ADDR_OFST           0x124
+#define S10_SYSMGR_UE_VAL_OFST            0x220
+#define S10_SYSMGR_UE_ADDR_OFST           0x224
 
 #define S10_DDR0_IRQ_MASK                 BIT(16)