linux-kernel - Re: [PATCH v5 2/2] spi-atmel: support inter-word delay

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Wed, 30 Jan 2019 08:15:56 +0000
From:   <Nicolas.Ferre@...rochip.com>
To:     <jonas@...rbonn.se>, <linux-kernel@...r.kernel.org>,
        <broonie@...nel.org>
CC:     <alexandre.belloni@...tlin.com>, <Ludovic.Desroches@...rochip.com>,
        <linux-spi@...r.kernel.org>,
        <linux-arm-kernel@...ts.infradead.org>,
        <Tudor.Ambarus@...rochip.com>
Subject: Re: [PATCH v5 2/2] spi-atmel: support inter-word delay

On 29/01/2019 at 21:55, Jonas Bonn wrote:
> If the SPI slave requires an inter-word delay, configure the DLYBCT
> register accordingly.
> 
> Tested on a SAMA5D2 board (derived from SAMA5D2-Xplained reference
> board).
> 
> Signed-off-by: Jonas Bonn <jonas@...rbonn.se>
> CC: Nicolas Ferre <nicolas.ferre@...rochip.com>
> CC: Mark Brown <broonie@...nel.org>
> CC: Alexandre Belloni <alexandre.belloni@...tlin.com>
> CC: Ludovic Desroches <ludovic.desroches@...rochip.com>
> CC: linux-spi@...r.kernel.org
> CC: linux-arm-kernel@...ts.infradead.org
> ---
>   drivers/spi/spi-atmel.c | 11 ++++++-----
>   1 file changed, 6 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
> index f53f0c5e63da..57cc7110f9e8 100644
> --- a/drivers/spi/spi-atmel.c
> +++ b/drivers/spi/spi-atmel.c
> @@ -1201,13 +1201,14 @@ static int atmel_spi_setup(struct spi_device *spi)
>   		csr |= SPI_BIT(CSAAT);
>   
>   	/* DLYBS is mostly irrelevant since we manage chipselect using GPIOs.
> -	 *
> -	 * DLYBCT would add delays between words, slowing down transfers.
> -	 * It could potentially be useful to cope with DMA bottlenecks, but
> -	 * in those cases it's probably best to just use a lower bitrate.
>   	 */
>   	csr |= SPI_BF(DLYBS, 0);
> -	csr |= SPI_BF(DLYBCT, 0);
> +
> +	/* DLYBCT adds delays between words.  This is useful for slow devices
> +	 * that need a bit of time to setup the next transfer.
> +	 */
> +	csr |= SPI_BF(DLYBCT,
> +			(as->spi_clk / 1000000 * spi->word_delay_us) >> 5);

Looks good to me:
Acked-by: Nicolas Ferre <nicolas.ferre@...rochip.com>


>   	asd = spi->controller_state;
>   	if (!asd) {
> 


-- 
Nicolas Ferre