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Date: Wed, 30 Jan 2019 21:14:03 +0800
From: Zhou Yanjie <zhouyanjie@...o.com>
To: linux-mips@...r.kernel.org
Cc: linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
paul.burton@...s.com, ralf@...ux-mips.org, jhogan@...nel.org,
robh+dt@...nel.org, ezequiel@...labora.co.uk, paul@...pouillou.net,
mark.rutland@....com, syq@...ian.org, jiaxun.yang@...goat.com,
772753199@...com, ulf.hansson@...aro.org, malat@...ian.org
Subject: [PATCH 1/2] dt-bindings: MIPS: Add doc about Ingenic CPU node.
Dt-bindings doc about CPU node of Ingenic XBurst based SOCs.
Signed-off-by: Zhou Yanjie <zhouyanjie@...o.com>
---
.../devicetree/bindings/mips/ingenic/ingenic,cpu.txt | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.txt
diff --git a/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.txt b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.txt
new file mode 100644
index 0000000..38e3cd3
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.txt
@@ -0,0 +1,17 @@
+Ingenic Soc CPU
+
+Required properties:
+- device_type: Must be "cpu".
+- compatible: One of:
+ - "ingenic,xburst".
+- reg: The number of the CPU.
+- next-level-cache: If there is a next level cache, point to it.
+
+Example:
+cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "ingenic,xburst";
+ reg = <0>;
+ next-level-cache = <&l2c>;
+};
+
--
2.7.4
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