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Message-ID: <1549009343.22634.4.camel@mtksdaap41>
Date: Fri, 1 Feb 2019 16:22:23 +0800
From: Weiyi Lu <weiyi.lu@...iatek.com>
To: Stephen Boyd <sboyd@...nel.org>
CC: Matthias Brugger <matthias.bgg@...il.com>,
Nicolas Boichat <drinkcat@...omium.org>,
Rob Herring <robh@...nel.org>,
Stephen Boyd <sboyd@...eaurora.org>,
James Liao <jamesjj.liao@...iatek.com>,
<srv_heupstream@...iatek.com>, <linux-kernel@...r.kernel.org>,
<stable@...r.kernel.org>, Fan Chen <fan.chen@...iatek.com>,
<linux-mediatek@...ts.infradead.org>, <linux-clk@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH v3 08/12] clk: mediatek: Add MT8183 clock support
On Fri, 2018-12-14 at 13:59 -0800, Stephen Boyd wrote:
> Quoting Weiyi Lu (2018-12-09 23:32:36)
> > + "apll2_ck"
> > +};
> > +
> > +static const struct mtk_mux top_muxes[] = {
> > + /* CLK_CFG_0 */
> > + MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_MUX_AXI, "axi_sel",
> > + axi_parents, 0x40,
> > + 0x44, 0x48, 0, 2, 7, 0x004, 0, CLK_IS_CRITICAL),
>
> Please document why CLK_IS_CRITICAL is being used everywhere it's used.
>
OK, I'll add some more comment at where critical clock data is declared.
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_MM, "mm_sel",
> > + mm_parents, 0x40,
> > + 0x44, 0x48, 8, 3, 15, 0x004, 1),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_IMG, "img_sel",
> > + img_parents, 0x40,
> > + 0x44, 0x48, 16, 3, 23, 0x004, 2),
> > + MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_CAM, "cam_sel",
>
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