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Message-ID: <20190201145414.GA22199@localhost.localdomain>
Date: Fri, 1 Feb 2019 07:54:14 -0700
From: Keith Busch <keith.busch@...el.com>
To: Takao Indoh <indou.takao@...fujitsu.com>
Cc: axboe@...com, hch@....de, sagi@...mberg.me,
linux-nvme@...ts.infradead.org, linux-kernel@...r.kernel.org,
Takao Indoh <indou.takao@...itsu.com>
Subject: Re: [PATCH] nvme: Enable acceleration feature of A64FX processor
On Fri, Feb 01, 2019 at 09:46:15PM +0900, Takao Indoh wrote:
> From: Takao Indoh <indou.takao@...itsu.com>
>
> Fujitsu A64FX processor has a feature to accelerate data transfer of
> internal bus by relaxed ordering. It is enabled when the bit 56 of dma
> address is set to 1.
Wait, what? RO is a standard PCIe TLP attribute. Why would we need this?
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