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Message-Id: <1549039612-28905-7-git-send-email-l.luba@partner.samsung.com>
Date: Fri, 1 Feb 2019 17:46:50 +0100
From: Lukasz Luba <l.luba@...tner.samsung.com>
To: devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-pm@...r.kernel.org, linux-samsung-soc@...r.kernel.org
Cc: b.zolnierkie@...sung.com, krzk@...nel.org, kgene@...nel.org,
cw00.choi@...sung.com, kyungmin.park@...sung.com,
m.szyprowski@...sung.com, s.nawrocki@...sung.com,
myungjoo.ham@...sung.com, Lukasz Luba <l.luba@...tner.samsung.com>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
linux-arm-kernel@...ts.infradead.org
Subject: [PATCH v4 6/8] DT: arm: exynos: add DMC device for exynos5422
Add description of Dynamic Memory Controller and PPMU counters.
They are used by exynos5422-dmc driver.
Signed-off-by: Lukasz Luba <l.luba@...tner.samsung.com>
---
arch/arm/boot/dts/exynos5420.dtsi | 78 +++++++++++++++++++++++++++
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 22 ++++++++
2 files changed, 100 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index aaff158..574d398 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -235,6 +235,36 @@
status = "disabled";
};
+ dmc: memory-controller@...20000 {
+ compatible = "samsung,exynos5422-dmc";
+ reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>,
+ <0x10030000 0x1000>, <0x10000000 0x1000>;
+ clocks = <&clock CLK_FOUT_SPLL>,
+ <&clock CLK_MOUT_SCLK_SPLL>,
+ <&clock CLK_FF_DOUT_SPLL2>,
+ <&clock CLK_FOUT_BPLL>,
+ <&clock CLK_MOUT_BPLL>,
+ <&clock CLK_SCLK_BPLL>,
+ <&clock CLK_MOUT_MX_MSPLL_CCORE>,
+ <&clock CLK_MOUT_MX_MSPLL_CCORE_PHY>,
+ <&clock CLK_MOUT_MCLK_CDREX>,
+ <&clock CLK_DOUT_CLK2X_PHY0>,
+ <&clock CLK_CLKM_PHY0>,
+ <&clock CLK_CLKM_PHY1>;
+ clock-names = "fout_spll",
+ "mout_sclk_spll",
+ "ff_dout_spll2",
+ "fout_bpll",
+ "mout_bpll",
+ "sclk_bpll",
+ "mout_mx_mspll_ccore",
+ "mout_mx_mspll_ccore_phy",
+ "mout_mclk_cdrex",
+ "dout_clk2x_phy0",
+ "clkm_phy0",
+ "clkm_phy1";
+ };
+
nocp_mem0_0: nocp@...a1000 {
compatible = "samsung,exynos5420-nocp";
reg = <0x10CA1000 0x200>;
@@ -271,6 +301,54 @@
status = "disabled";
};
+ ppmu_dmc0_0: ppmu@...00000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x10d00000 0x2000>;
+ clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
+ clock-names = "ppmu";
+ events {
+ ppmu_event_dmc0_0: ppmu-event3-dmc0_0 {
+ event-name = "ppmu-event3-dmc0_0";
+ };
+ };
+ };
+
+ ppmu_dmc0_1: ppmu@...10000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x10d10000 0x2000>;
+ clocks = <&clock CLK_PCLK_PPMU_DREX0_1>;
+ clock-names = "ppmu";
+ events {
+ ppmu_event_dmc0_1: ppmu-event3-dmc0_1 {
+ event-name = "ppmu-event3-dmc0_1";
+ };
+ };
+ };
+
+ ppmu_dmc1_0: ppmu@...10000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x10d60000 0x2000>;
+ clocks = <&clock CLK_PCLK_PPMU_DREX1_0>;
+ clock-names = "ppmu";
+ events {
+ ppmu_event_dmc1_0: ppmu-event3-dmc1_0 {
+ event-name = "ppmu-event3-dmc1_0";
+ };
+ };
+ };
+
+ ppmu_dmc1_1: ppmu@...70000 {
+ compatible = "samsung,exynos-ppmu";
+ reg = <0x10d70000 0x2000>;
+ clocks = <&clock CLK_PCLK_PPMU_DREX1_1>;
+ clock-names = "ppmu";
+ events {
+ ppmu_event_dmc1_1: ppmu-event3-dmc1_1 {
+ event-name = "ppmu-event3-dmc1_1";
+ };
+ };
+ };
+
gsc_pd: power-domain@...44000 {
compatible = "samsung,exynos4210-pd";
reg = <0x10044000 0x20>;
diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
index bf09eab..e2b59e9 100644
--- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
+++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi
@@ -127,6 +127,12 @@
cpu-supply = <&buck2_reg>;
};
+&dmc {
+ devfreq-events = <&ppmu_dmc0_0>, <&ppmu_dmc0_1>,
+ <&ppmu_dmc1_0>, <&ppmu_dmc1_1>;
+ status = "okay";
+};
+
&hsi2c_4 {
status = "okay";
@@ -535,6 +541,22 @@
};
};
+&ppmu_dmc0_0 {
+ status = "okay";
+};
+
+&ppmu_dmc0_1 {
+ status = "okay";
+};
+
+&ppmu_dmc1_0 {
+ status = "okay";
+};
+
+&ppmu_dmc1_1 {
+ status = "okay";
+};
+
&tmu_cpu0 {
vtmu-supply = <&ldo7_reg>;
};
--
2.7.4
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