linux-kernel - Re: [PATCH 1/3] mmc: sunxi: Disable HS-DDR mode for H5 eMMC controller by default

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Message-ID: <20190204093214.7zbomq5cddacdrmj@flea>
Date:   Mon, 4 Feb 2019 10:32:14 +0100
From:   Maxime Ripard <maxime.ripard@...tlin.com>
To:     Chen-Yu Tsai <wens@...e.org>
Cc:     Ulf Hansson <ulf.hansson@...aro.org>, linux-mmc@...r.kernel.org,
        linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-sunxi@...glegroups.com,
        Chris Blake <chrisrblake93@...il.com>, stable@...r.kernel.org
Subject: Re: [PATCH 1/3] mmc: sunxi: Disable HS-DDR mode for H5 eMMC
 controller by default

On Sun, Feb 03, 2019 at 11:56:26PM +0800, Chen-Yu Tsai wrote:
> Some H5 boards seem to not have proper trace lengths for eMMC to be able
> to use the default setting for the delay chains under HS-DDR mode. These
> include the Bananapi M2+ H5 and NanoPi NEO Core2. However the Libre
> Computer ALL-H3-CC-H5 works just fine.
> 
> For the H5 (at least for now), default to not enabling HS-DDR modes in
> the driver, and expect the device tree to signal HS-DDR capability on
> boards that work.
> 
> Reported-by: Chris Blake <chrisrblake93@...il.com>
> Fixes: 07bafc1e3536 ("mmc: sunxi: Use new timing mode for A64 eMMC controller")
> Cc: <stable@...r.kernel.org>
> Signed-off-by: Chen-Yu Tsai <wens@...e.org>

Acked-by: Maxime Ripard <maxime.ripard@...tlin.com>

Maxime

-- 
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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