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Message-ID: <5C5980B6.4010502@ti.com>
Date: Tue, 5 Feb 2019 14:25:26 +0200
From: Roger Quadros <rogerq@...com>
To: <t-kristo@...com>
CC: <robh+dt@...nel.org>, <linux-arm-kernel@...ts.infradead.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
Nishanth Menon <nm@...com>, Lokesh Vutla <lokeshvutla@...com>,
"Andrew F . Davis" <afd@...com>
Subject: Re: [PATCH] arm64: dts: ti: k3-am65: Add MSMC RAM node
Tero,
On 11/01/19 11:44, Roger Quadros wrote:
> The AM65 SoC has 2MB MSMC RAM. Add this as a mmio-sram
> node so drivers can use it via genpool API.
>
> Following areas are marked reserved:
> - Lower 128KB for ATF
> - 64KB@...0000 for SYSFW
> - Upper 1MB for cache
>
> The reserved locations are subject to change at runtime by
> the bootloader.
>
> Cc: Nishanth Menon <nm@...com>
> Cc: Lokesh Vutla <lokeshvutla@...com>
> Cc: Andrew F. Davis <afd@...com>
> Signed-off-by: Roger Quadros <rogerq@...com>
Is this patch good to pick for -next?
cheers,
-roger
> ---
> arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> index 272cf8f..5a18150 100644
> --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> @@ -6,6 +6,26 @@
> */
>
> &cbass_main {
> + msmc_ram: sram@...00000 {
> + compatible = "mmio-sram";
> + reg = <0x0 0x70000000 0x0 0x200000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x0 0x70000000 0x200000>;
> +
> + atf-sram@0 {
> + reg = <0x0 0x20000>;
> + };
> +
> + sysfw-sram@...00 {
> + reg = <0xf0000 0x10000>;
> + };
> +
> + l3cache-sram@...000 {
> + reg = <0x100000 0x100000>;
> + };
> + };
> +
> gic500: interrupt-controller@...0000 {
> compatible = "arm,gic-v3";
> #address-cells = <2>;
>
--
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