linux-kernel - Re: linux-next: manual merge of the mips tree with the mips-fixes tree

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Tue, 5 Feb 2019 23:35:31 +0000
From:   Paul Burton <paul.burton@...s.com>
To:     Stephen Rothwell <sfr@...b.auug.org.au>
CC:     Ralf Baechle <ralf@...ux-mips.org>,
        James Hogan <jhogan@...nel.org>,
        Linux Next Mailing List <linux-next@...r.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Huacai Chen <chenhc@...ote.com>,
        Huang Pei <huangpei@...ngson.cn>
Subject: Re: linux-next: manual merge of the mips tree with the mips-fixes
 tree

Hi Stephen,

On Wed, Feb 06, 2019 at 09:17:36AM +1100, Stephen Rothwell wrote:
> Hi all,
> 
> Today's linux-next merge of the mips tree got conflicts in:
> 
>   arch/mips/include/asm/barrier.h
>   arch/mips/include/asm/pgtable.h
> 
> between commit:
> 
>   e02e07e3127d ("MIPS: Loongson: Introduce and use loongson_llsc_mb()")
> 
> from the mips-fixes tree and commits:
> 
>   535113896e80 ("MIPS: Add GINVT instruction helpers")
>   82f4f66ddf11 ("MIPS: Remove open-coded cmpxchg() in set_pte()")
> 
> from the mips tree.
> 
> I fixed it up (see below and for the latter file, I used the mips tree
> version but wondered if cmpxchg() needs the fixups from the mips-fixes
> tree commit)

Thanks - that looks good.

cmpxchg() doesn't need the added loongson_llsc_mb() barrier that
set_pte() has in mips-fixes because for the affected Loongson 3
configurations the smp_mb__before_llsc() that cmpxchg() already contains
is equivalent (both will emit a "sync 0" instruction).

Thanks,
    Paul