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Message-ID: <8b0b85cb-c08e-3426-fe34-0b6dfc9c0cc4@intel.com>
Date:   Wed, 6 Feb 2019 16:33:54 -0800
From:   Dave Hansen <dave.hansen@...el.com>
To:     "Luck, Tony" <tony.luck@...el.com>, Ingo Molnar <mingo@...nel.org>
Cc:     Linus Torvalds <torvalds@...ux-foundation.org>,
        linux-kernel@...r.kernel.org,
        Peter Zijlstra <a.p.zijlstra@...llo.nl>,
        Dave Hansen <dave.hansen@...ux.intel.com>,
        Andy Lutomirski <luto@...nel.org>,
        Borislav Petkov <bp@...en8.de>,
        Thomas Gleixner <tglx@...utronix.de>,
        Rik van Riel <riel@...riel.com>
Subject: Re: [GIT PULL] x86/mm changes for v4.21

On 2/6/19 4:17 PM, Luck, Tony wrote:
> [   93.491692] RAX: 0000000000000000 RBX: 0000000000000000 RCX: ffff99623f2c3f70
> [   93.499658] RDX: 2e6b58da00000121 RSI: 0000000000000000 RDI: 7fff9981feeab000
...
> Potentially the problem might be a non-canonical address passed down
> by the machine check recovery code to switch the page with the error
> to uncacheable. Perhaps the refactored code is now using that in the
> 
> 	invpcid (%rcx),%rax
> 
> instruction that gets the #GP fault?

That looks probable.  RDI even has the non-canonical address still in it
(RCX is pointing to the stack, btw).

I think there's an option to dump the trace buffers at panic time.  You
might want to enable the TLB flush tracing:

	/sys/kernel/debug/tracing/events/tlb/tlb_flush

and see if we get a suspect flush captured just before the #GP.

I wonder if the patches that you bisected to just changed the flushing
from being CR3-based (and not taking an address) to being INVPCID-based,
and taking an address that is sensitive to canonicality.

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