linux-kernel - Re: [RFC 4/5] arm64: dts: Add nodes for PCIe IP blocks

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <CAHQ1cqGOtGb1mt7BCm_DaKoJn=6=atauipgt6Dg2-doSEoj_tg@mail.gmail.com>
Date:   Thu, 7 Feb 2019 13:22:23 -0800
From:   Andrey Smirnov <andrew.smirnov@...il.com>
To:     Lucas Stach <l.stach@...gutronix.de>
Cc:     Shawn Guo <shawnguo@...nel.org>,
        Fabio Estevam <fabio.estevam@....com>,
        Chris Healy <cphealy@...il.com>,
        Leonard Crestez <leonard.crestez@....com>,
        "A.s. Dong" <aisheng.dong@....com>,
        Richard Zhu <hongxing.zhu@....com>,
        dl-linux-imx <linux-imx@....com>,
        linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
        linux-kernel <linux-kernel@...r.kernel.org>
Subject: Re: [RFC 4/5] arm64: dts: Add nodes for PCIe IP blocks

On Thu, Feb 7, 2019 at 6:27 AM Lucas Stach <l.stach@...gutronix.de> wrote:
>
> Am Donnerstag, den 31.01.2019, 12:43 -0800 schrieb Andrey Smirnov:
> > Add nodes for two PCIe controllers found on i.MX8MQ.
> >
> > > Signed-off-by: Andrey Smirnov <andrew.smirnov@...il.com>
> > > Cc: Shawn Guo <shawnguo@...nel.org>
> > > Cc: Fabio Estevam <fabio.estevam@....com>
> > > Cc: Chris Healy <cphealy@...il.com>
> > > Cc: Lucas Stach <l.stach@...gutronix.de>
> > > Cc: Leonard Crestez <leonard.crestez@....com>
> > > Cc: "A.s. Dong" <aisheng.dong@....com>
> > > Cc: Richard Zhu <hongxing.zhu@....com>
> > Cc: linux-imx@....com
> > Cc: linux-arm-kernel@...ts.infradead.org
> > Cc: linux-kernel@...r.kernel.org
> > ---
> >  arch/arm64/boot/dts/freescale/imx8mq.dtsi | 68 +++++++++++++++++++++++
> >  1 file changed, 68 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > index 89babc531380..d20e5c7e21a3 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> > @@ -6,6 +6,7 @@
> >
> >  #include <dt-bindings/clock/imx8mq-clock.h>
> >  #include <dt-bindings/power/imx8mq-power.h>
> > +#include <dt-bindings/reset/imx8mq-reset.h>
> >  #include <dt-bindings/gpio/gpio.h>
> >  #include <dt-bindings/interrupt-controller/arm-gic.h>
> >  #include "imx8mq-pinfunc.h"
> > @@ -539,6 +540,73 @@
> >                       };
> >
> >       };
> >
> > +             pcie0: pcie@...00000 {
> > +                     compatible = "fsl,imx8mq-pcie";
> > +                     reg = <0x33800000 0x400000>,
> > +                           <0x1ff00000 0x80000>;
> > +                     reg-names = "dbi", "config";
> > +                     #address-cells = <3>;
> > +                     #size-cells = <2>;
> > +                     device_type = "pci";
> > +                     bus-range = <0x00 0xff>;
> > +                     ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000 /* downstream I/O 64KB */
> > +                               0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
> > +                     num-lanes = <1>;
> > +                     interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
> > +                                  <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
>
> I don't think this IRQ is documented in any binding yet.
>

A leftover from vendor tree. Will drop in v2.

> > +                     interrupt-names = "msi";
> > +                     #interrupt-cells = <1>;
> > +                     interrupt-map-mask = <0 0 0 0x7>;
> > +                     interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
> > +                                     <0 0 0 2 &gic GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
> > +                                     <0 0 0 3 &gic GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
> > +                                     <0 0 0 4 &gic GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
> > +                     clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
> > +                              <&clk IMX8MQ_CLK_PCIE1_AUX>,
>
> This is not the PCIe bus clock. The bus clock is whatever drives the
> ref clock of the external bus. So on the i.MX8M-EVK this would be the
> fixed clock generated by U1302.
>
> The right thing to properly describe the HW is to extend the PCIe
> driver to look for the aux clock on i.MX8M, just like we do with the
> axi_inbound_clk on i.MX6SX.
>

OK, will update it in v2 and send a corresponding patch to PCI tree
once everything is agreed upon.

Thanks,
Andrey Smirnov