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Message-ID: <CAFZiPx0faPHN1mqPV28XTZfOxA2GgDPuc=RVdXEiGGNAUe=Fxw@mail.gmail.com>
Date: Fri, 8 Feb 2019 18:11:15 +0530
From: Subrahmanya Lingappa <l.subrahmanya@...iveil.co.in>
To: "Z.q. Hou" <zhiqiang.hou@....com>
Cc: "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"bhelgaas@...gle.com" <bhelgaas@...gle.com>,
"robh+dt@...nel.org" <robh+dt@...nel.org>,
"mark.rutland@....com" <mark.rutland@....com>,
"shawnguo@...nel.org" <shawnguo@...nel.org>,
Leo Li <leoyang.li@....com>,
"lorenzo.pieralisi@....com" <lorenzo.pieralisi@....com>,
"catalin.marinas@....com" <catalin.marinas@....com>,
"will.deacon@....com" <will.deacon@....com>,
Mingkai Hu <mingkai.hu@....com>,
"M.h. Lian" <minghuan.lian@....com>,
Xiaowei Bao <xiaowei.bao@....com>
Subject: Re: [PATCHv3 17/27] PCI: mobiveil: fix the checking of valid device
ZQ,
On Tue, Jan 29, 2019 at 1:40 PM Z.q. Hou <zhiqiang.hou@....com> wrote:
>
> From: Hou Zhiqiang <Zhiqiang.Hou@....com>
>
> Avoid to issue CFG transactions to link partner when the PCIe
> link is not up. And allow CFG transactions to all functions of
> Endpoint implemented multiple functions.
>
> Fixes: 9af6bcb11e12 ("PCI: mobiveil: Add Mobiveil PCIe Host
> Bridge IP driver")
> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@....com>
> Reviewed-by: Minghuan Lian <Minghuan.Lian@....com>
> ---
> V3:
> - No change
>
> drivers/pci/controller/mobiveil/pcie-mobiveil-host.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> index dc5324d94466..1ae82e790562 100644
> --- a/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-host.c
> @@ -29,6 +29,10 @@ static bool mobiveil_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
> {
> struct mobiveil_pcie *pcie = bus->sysdata;
>
> + /* If there is no link, then there is no device */
> + if (bus->number > pcie->rp.root_bus_nr && !mobiveil_pcie_link_up(pcie))
> + return false;
> +
> /* Only one device down on each root port */
> if ((bus->number == pcie->rp.root_bus_nr) && (devfn > 0))
> return false;
> @@ -37,7 +41,7 @@ static bool mobiveil_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
> * Do not read more than one device on the bus directly
> * attached to RC
> */
> - if ((bus->primary == pcie->rp.root_bus_nr) && (devfn > 0))
> + if ((bus->primary == pcie->rp.root_bus_nr) && (PCI_SLOT(devfn) > 0))
here change "primary" to "number", as it's a bug in the original driver too.
> return false;
>
> return true;
> --
> 2.17.1
>
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