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Message-ID: <5c93782e-623c-707a-6fe0-dfe78d14a600@linux.intel.com>
Date: Mon, 11 Feb 2019 13:48:43 -0800
From: sathyanarayanan kuppuswamy
<sathyanarayanan.kuppuswamy@...ux.intel.com>
To: bhelgaas@...gle.com, joro@...tes.org, dwmw2@...radead.org
Cc: linux-pci@...r.kernel.org, iommu@...ts.linux-foundation.org,
linux-kernel@...r.kernel.org, ashok.raj@...el.com,
jacob.jun.pan@...el.com, keith.busch@...el.com
Subject: Re: [PATCH v2 0/2] Add page alignment check in Intel IOMMU.
On 2/11/19 1:43 PM, sathyanarayanan.kuppuswamy@...ux.intel.com wrote:
> From: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@...ux.intel.com>
>
> As per Intel vt-d specification, Rev 3.0 (section 7.5.1.1, title "Page Request Descriptor"), Intel IOMMU Page Request Descriptor only provides bits[63:12] of the page address. Hence its required to enforce that the device will only send page request with page-aligned address. So, this patch set adds support to verify whether the device uses page aligned address before enabling the ATS service in Intel IOMMU driver.
Please ignore this mail. This is my older copy.
>
> Kuppuswamy Sathyanarayanan (2):
> PCI: ATS: Add function to check ATS page alignment status.
> iommu/vt-d: Enable ATS only if the device uses page aligned address.
>
> drivers/iommu/intel-iommu.c | 1 +
> drivers/pci/ats.c | 24 ++++++++++++++++++++++++
> include/linux/pci.h | 2 ++
> include/uapi/linux/pci_regs.h | 1 +
> 4 files changed, 28 insertions(+)
>
--
Sathyanarayanan Kuppuswamy
Linux kernel developer
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