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Message-ID: <20190212183415.GI7875@lahna.fi.intel.com>
Date:   Tue, 12 Feb 2019 20:34:15 +0200
From:   Mika Westerberg <mika.westerberg@...ux.intel.com>
To:     Lukas Wunner <lukas@...ner.de>
Cc:     linux-kernel@...r.kernel.org,
        Michael Jamet <michael.jamet@...el.com>,
        Yehezkel Bernat <YehezkelShB@...il.com>,
        Andreas Noever <andreas.noever@...il.com>,
        Andy Shevchenko <andriy.shevchenko@...ux.intel.com>
Subject: Re: [PATCH v2 16/28] thunderbolt: Discover preboot PCIe paths the
 boot firmware established

On Tue, Feb 12, 2019 at 06:49:42PM +0100, Lukas Wunner wrote:
> On Wed, Feb 06, 2019 at 04:17:26PM +0300, Mika Westerberg wrote:
> >  		/* dword 0 */
> >  		hop.next_hop = path->hops[i].next_hop_index;
> >  		hop.out_port = path->hops[i].out_port->port;
> > -		/* TODO: figure out why these are good values */
> > -		hop.initial_credits = (i == path->path_length - 1) ? 16 : 7;
> > +		hop.initial_credits = path->hops[i].initial_credits;
> >  		hop.unknown1 = 0;
> >  		hop.enable = 1;
> [...]
> > @@ -78,6 +78,74 @@ static void tb_pci_init_path(struct tb_path *path)
> >  	path->weight = 1;
> >  	path->drop_packages = 0;
> >  	path->nfc_credits = 0;
> > +	path->hops[0].initial_credits = 7;
> > +	path->hops[1].initial_credits = 16;
> 
> I guess Andreas' algorithm (the last hop in the path is assigned
> 16 and all the ones before are assigned 7) was reverse-engineered
> from Apple's driver.  The fact that this algorithm works for paths
> of arbitrary length could indicate that Apple indeed does establish
> tunnels between non-adjacent switches.

We do it as well for DP and DMA paths in subsequent patches. For those
there are NULL ports in the middle which get assigned different amount
of credits. PCIe paths on the other hand only need two hops when we
daisy-chain them in this patch series.

> Also, why are these good values?  (You've deleted the comment.)

To be honest, I don't know all the details. Credits are used for flow
control to make sure receiving port always has enough buffers before
sending port can send more packets (assuming the path is using flow
control). I don't know where 7 and 16 came but they seem to work pretty
well for PCIe path so I kept using them.

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