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Message-ID: <20190212071128.GG26747@infradead.org>
Date: Mon, 11 Feb 2019 23:11:28 -0800
From: Christoph Hellwig <hch@...radead.org>
To: Anup Patel <anup@...infault.org>
Cc: Palmer Dabbelt <palmer@...ive.com>,
Albert Ou <aou@...s.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Thomas Gleixner <tglx@...utronix.de>,
Jason Cooper <jason@...edaemon.net>,
Marc Zyngier <marc.zyngier@....com>,
Christoph Hellwig <hch@...radead.org>,
Atish Patra <atish.patra@....com>,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v5 1/5] irqchip: sifive-plic: Pre-compute context hart
base and enable base
On Sat, Jan 19, 2019 at 11:26:21AM +0530, Anup Patel wrote:
> This patch does following optimizations:
> 1. Pre-compute hart base for each context handler
> 2. Pre-compute enable base for each context handler
> 3. Have enable lock for each context handler instead
> of global plic_toggle_lock
>
> Signed-off-by: Anup Patel <anup@...infault.org>
> ---
> drivers/irqchip/irq-sifive-plic.c | 47 ++++++++++++++-----------------
> 1 file changed, 21 insertions(+), 26 deletions(-)
I don't really see the point, but the code looks clean enough and
removes a few lines, so:
Reviewed-by: Christoph Hellwig <hch@....de>
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